| Message ID | 20230427142934.55435-5-francesco@dolcini.it (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/bridge: tc358768: various fixes on PLL calculation and DSI timings | expand |
On Thu, Apr 27, 2023 at 4:35 PM Francesco Dolcini <francesco@dolcini.it> wrote: > > From: Francesco Dolcini <francesco.dolcini@toradex.com> > > Correct computation of TCLK_ZEROCNT register. > > This register must be set to a value that ensure that > (TCLK-PREPARECNT + TCLK-ZERO) > 300ns > > with the actual value of (TCLK-PREPARECNT + TCLK-ZERO) being > > (1 to 2) + (TCLK_ZEROCNT + 1)) x HSByteClkCycle + (PHY output delay) > > with PHY output delay being about > > (2 to 3) x MIPIBitClk cycle in the BitClk conversion. > > Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") > Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> > --- > drivers/gpu/drm/bridge/tc358768.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c > index dba1bf3912f1..aff400c36066 100644 > --- a/drivers/gpu/drm/bridge/tc358768.c > +++ b/drivers/gpu/drm/bridge/tc358768.c > @@ -742,10 +742,10 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) > > /* 38ns < TCLK_PREPARE < 95ns */ > val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; > - /* TCLK_PREPARE > 300ns */ > - val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk), > - dsibclk_nsk); > - val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8; > + /* TCLK_PREPARE + TCLK_ZERO > 300ns */ > + val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), > + dsibclk_nsk) - 2; > + val |= val2 << 8; > dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val); > tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); > > -- > 2.25.1 > Reviewed-by: Robert Foss <rfoss@kernel.org>
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index dba1bf3912f1..aff400c36066 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -742,10 +742,10 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) /* 38ns < TCLK_PREPARE < 95ns */ val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; - /* TCLK_PREPARE > 300ns */ - val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk), - dsibclk_nsk); - val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8; + /* TCLK_PREPARE + TCLK_ZERO > 300ns */ + val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), + dsibclk_nsk) - 2; + val |= val2 << 8; dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val); tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);