| Message ID | 20230509103033.11285-4-andy.chiu@sifive.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | riscv: Add vector ISA support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD ac9a78681b92 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 249 this patch: 249 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 918 this patch: 918 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | CHECK: Prefer using the BIT macro |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
Am Dienstag, 9. Mai 2023, 12:30:12 CEST schrieb Andy Chiu: > Probing kernel support for Vector extension is available now. > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > --- > Documentation/riscv/hwprobe.rst | 10 ++++++++++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ > arch/riscv/kernel/sys_riscv.c | 9 +++++++++ > 4 files changed, 23 insertions(+), 1 deletion(-) > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > index 9f0dd62dcb5d..b8755e180fbf 100644 > --- a/Documentation/riscv/hwprobe.rst > +++ b/Documentation/riscv/hwprobe.rst > @@ -53,6 +53,9 @@ The following keys are defined: > programs (it may still be executed in userspace via a > kernel-controlled mechanism such as the vDSO). > > + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: Support for Vector extension, as > + defined by verion 1.0 of the RISC-V Vector extension. ^^ version [missing the S] > + > * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions > that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: > base system behavior. > @@ -64,6 +67,13 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > by version 2.2 of the RISC-V ISA manual. > > +* :c:macro:`RISCV_HWPROBE_KEY_V_EXT_0`: A bitmask containing the extensions > + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: base > + system behavior. > + > + * :c:macro:`RISCV_HWPROBE_V`: The V extension is supported, as defined by > + version 1.0 of the RISC-V Vector extension manual. > + this seems to be doubling the RISCV_HWPROBE_BASE_BEHAVIOR_V state without adding additional information? Both essentially tell the system that V extension "defined by verion 1.0 of the RISC-V Vector extension" is supported. I don't question that we'll probably need a key for deeper vector- specifics but I guess I'd the commit message should definitly explain why there is a duplication here. > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > index 78936f4ff513..39df8604fea1 100644 > --- a/arch/riscv/include/asm/hwprobe.h > +++ b/arch/riscv/include/asm/hwprobe.h > @@ -8,6 +8,6 @@ > > #include <uapi/asm/hwprobe.h> > > -#define RISCV_HWPROBE_MAX_KEY 5 > +#define RISCV_HWPROBE_MAX_KEY 6 > > #endif > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 8d745a4ad8a2..93a7fd3fd341 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -22,6 +22,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_MIMPID 2 > #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 > #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) > +#define RISCV_HWPROBE_BASE_BEHAVIOR_V (1 << 1) > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > #define RISCV_HWPROBE_IMA_FD (1 << 0) > #define RISCV_HWPROBE_IMA_C (1 << 1) > @@ -32,6 +33,8 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > +#define RISCV_HWPROBE_KEY_V_EXT_0 6 > +#define RISCV_HWPROBE_V (1 << 0) > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > #endif > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > index 5db29683ebee..6280a7f778b3 100644 > --- a/arch/riscv/kernel/sys_riscv.c > +++ b/arch/riscv/kernel/sys_riscv.c > @@ -10,6 +10,7 @@ > #include <asm/cpufeature.h> > #include <asm/hwprobe.h> > #include <asm/sbi.h> > +#include <asm/vector.h> > #include <asm/switch_to.h> > #include <asm/uaccess.h> > #include <asm/unistd.h> > @@ -161,6 +162,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > */ > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; > + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_V; Doesn't this also need a if (has_vector()) Heiko > break; > > case RISCV_HWPROBE_KEY_IMA_EXT_0: > @@ -173,6 +175,13 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > > break; > > + case RISCV_HWPROBE_KEY_V_EXT_0: > + pair->value = 0; > + if (has_vector()) > + pair->value |= RISCV_HWPROBE_V; > + > + break; > + > case RISCV_HWPROBE_KEY_CPUPERF_0: > pair->value = hwprobe_misaligned(cpus); > break; >
On Tue, May 9, 2023 at 7:05 PM Heiko Stübner <heiko@sntech.de> wrote: > > Am Dienstag, 9. Mai 2023, 12:30:12 CEST schrieb Andy Chiu: > > Probing kernel support for Vector extension is available now. > > > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > > --- > > Documentation/riscv/hwprobe.rst | 10 ++++++++++ > > arch/riscv/include/asm/hwprobe.h | 2 +- > > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ > > arch/riscv/kernel/sys_riscv.c | 9 +++++++++ > > 4 files changed, 23 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > > index 9f0dd62dcb5d..b8755e180fbf 100644 > > --- a/Documentation/riscv/hwprobe.rst > > +++ b/Documentation/riscv/hwprobe.rst > > @@ -53,6 +53,9 @@ The following keys are defined: > > programs (it may still be executed in userspace via a > > kernel-controlled mechanism such as the vDSO). > > > > + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: Support for Vector extension, as > > + defined by verion 1.0 of the RISC-V Vector extension. > > ^^ version [missing the S] > > > + > > * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions > > that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: > > base system behavior. > > @@ -64,6 +67,13 @@ The following keys are defined: > > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > > by version 2.2 of the RISC-V ISA manual. > > > > +* :c:macro:`RISCV_HWPROBE_KEY_V_EXT_0`: A bitmask containing the extensions > > + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: base > > + system behavior. > > + > > + * :c:macro:`RISCV_HWPROBE_V`: The V extension is supported, as defined by > > + version 1.0 of the RISC-V Vector extension manual. > > + > > this seems to be doubling the RISCV_HWPROBE_BASE_BEHAVIOR_V state without > adding additional information? Both essentially tell the system that > V extension "defined by verion 1.0 of the RISC-V Vector extension" is supported. I was thinking that RISCV_HWPROBE_BASE_BEHAVIOR_V indicates the kernel has a probe for vector (just like RISCV_HWPROBE_BASE_BEHAVIOR_IMA) and RISCV_HWPROBE_KEY_V_EXT_0 is where the kernel reports what exactly the extension is. This maps to the condition matching of F,D, and C in IMA. If that is not the case then I think there is no need for this entry. > > I don't question that we'll probably need a key for deeper vector- > specifics but I guess I'd the commit message should definitly explain > why there is a duplication here. I suppose something like Zvfh should fall into the category of RISCV_HWPROBE_KEY_V_EXT_0. I will add this example into the commit message if you agree that is a good example. > > > > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > > information about the selected set of processors. > > > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > > index 78936f4ff513..39df8604fea1 100644 > > --- a/arch/riscv/include/asm/hwprobe.h > > +++ b/arch/riscv/include/asm/hwprobe.h > > @@ -8,6 +8,6 @@ > > > > #include <uapi/asm/hwprobe.h> > > > > -#define RISCV_HWPROBE_MAX_KEY 5 > > +#define RISCV_HWPROBE_MAX_KEY 6 > > > > #endif > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > index 8d745a4ad8a2..93a7fd3fd341 100644 > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > @@ -22,6 +22,7 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_KEY_MIMPID 2 > > #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 > > #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) > > +#define RISCV_HWPROBE_BASE_BEHAVIOR_V (1 << 1) > > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > > #define RISCV_HWPROBE_IMA_FD (1 << 0) > > #define RISCV_HWPROBE_IMA_C (1 << 1) > > @@ -32,6 +33,8 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) > > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > > +#define RISCV_HWPROBE_KEY_V_EXT_0 6 > > +#define RISCV_HWPROBE_V (1 << 0) > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > > > #endif > > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > > index 5db29683ebee..6280a7f778b3 100644 > > --- a/arch/riscv/kernel/sys_riscv.c > > +++ b/arch/riscv/kernel/sys_riscv.c > > @@ -10,6 +10,7 @@ > > #include <asm/cpufeature.h> > > #include <asm/hwprobe.h> > > #include <asm/sbi.h> > > +#include <asm/vector.h> > > #include <asm/switch_to.h> > > #include <asm/uaccess.h> > > #include <asm/unistd.h> > > @@ -161,6 +162,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > > */ > > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > > pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; > > + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_V; > > Doesn't this also need a > if (has_vector()) > If the RISCV_HWPROBE_KEY_BASE_BEHAVIOR part just tells whether hwprobe supports probing of a set of extensions then I think we should not add the if statement here, but maybe I misunderstood something.. > > Heiko > > > break; > > > > case RISCV_HWPROBE_KEY_IMA_EXT_0: > > @@ -173,6 +175,13 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > > > > break; > > > > + case RISCV_HWPROBE_KEY_V_EXT_0: > > + pair->value = 0; > > + if (has_vector()) > > + pair->value |= RISCV_HWPROBE_V; > > + > > + break; > > + > > case RISCV_HWPROBE_KEY_CPUPERF_0: > > pair->value = hwprobe_misaligned(cpus); > > break; > > > > > > Thanks, Andy
On Tue, May 9, 2023 at 9:41 AM Andy Chiu <andy.chiu@sifive.com> wrote: > > On Tue, May 9, 2023 at 7:05 PM Heiko Stübner <heiko@sntech.de> wrote: > > > > Am Dienstag, 9. Mai 2023, 12:30:12 CEST schrieb Andy Chiu: > > > Probing kernel support for Vector extension is available now. > > > > > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > > > --- > > > Documentation/riscv/hwprobe.rst | 10 ++++++++++ > > > arch/riscv/include/asm/hwprobe.h | 2 +- > > > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ > > > arch/riscv/kernel/sys_riscv.c | 9 +++++++++ > > > 4 files changed, 23 insertions(+), 1 deletion(-) > > > > > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > > > index 9f0dd62dcb5d..b8755e180fbf 100644 > > > --- a/Documentation/riscv/hwprobe.rst > > > +++ b/Documentation/riscv/hwprobe.rst > > > @@ -53,6 +53,9 @@ The following keys are defined: > > > programs (it may still be executed in userspace via a > > > kernel-controlled mechanism such as the vDSO). > > > > > > + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: Support for Vector extension, as > > > + defined by verion 1.0 of the RISC-V Vector extension. > > > > ^^ version [missing the S] > > > > > + > > > * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions > > > that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: > > > base system behavior. > > > @@ -64,6 +67,13 @@ The following keys are defined: > > > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > > > by version 2.2 of the RISC-V ISA manual. > > > > > > +* :c:macro:`RISCV_HWPROBE_KEY_V_EXT_0`: A bitmask containing the extensions > > > + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: base > > > + system behavior. > > > + > > > + * :c:macro:`RISCV_HWPROBE_V`: The V extension is supported, as defined by > > > + version 1.0 of the RISC-V Vector extension manual. > > > + > > > > this seems to be doubling the RISCV_HWPROBE_BASE_BEHAVIOR_V state without > > adding additional information? Both essentially tell the system that > > V extension "defined by verion 1.0 of the RISC-V Vector extension" is supported. > > I was thinking that RISCV_HWPROBE_BASE_BEHAVIOR_V indicates the kernel > has a probe for vector (just like RISCV_HWPROBE_BASE_BEHAVIOR_IMA) and > RISCV_HWPROBE_KEY_V_EXT_0 is where the kernel reports what exactly the > extension is. This maps to the condition matching of F,D, and C in > IMA. If that is not the case then I think there is no need for this > entry. > > > > > I don't question that we'll probably need a key for deeper vector- > > specifics but I guess I'd the commit message should definitly explain > > why there is a duplication here. > > I suppose something like Zvfh should fall into the category of > RISCV_HWPROBE_KEY_V_EXT_0. I will add this example into the commit > message if you agree that is a good example. > > > > > > > > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > > > information about the selected set of processors. > > > > > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > > > index 78936f4ff513..39df8604fea1 100644 > > > --- a/arch/riscv/include/asm/hwprobe.h > > > +++ b/arch/riscv/include/asm/hwprobe.h > > > @@ -8,6 +8,6 @@ > > > > > > #include <uapi/asm/hwprobe.h> > > > > > > -#define RISCV_HWPROBE_MAX_KEY 5 > > > +#define RISCV_HWPROBE_MAX_KEY 6 > > > > > > #endif > > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > > index 8d745a4ad8a2..93a7fd3fd341 100644 > > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > > @@ -22,6 +22,7 @@ struct riscv_hwprobe { > > > #define RISCV_HWPROBE_KEY_MIMPID 2 > > > #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 > > > #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) > > > +#define RISCV_HWPROBE_BASE_BEHAVIOR_V (1 << 1) > > > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > > > #define RISCV_HWPROBE_IMA_FD (1 << 0) > > > #define RISCV_HWPROBE_IMA_C (1 << 1) > > > @@ -32,6 +33,8 @@ struct riscv_hwprobe { > > > #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) > > > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > > > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > > > +#define RISCV_HWPROBE_KEY_V_EXT_0 6 > > > +#define RISCV_HWPROBE_V (1 << 0) > > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > > > > > #endif > > > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > > > index 5db29683ebee..6280a7f778b3 100644 > > > --- a/arch/riscv/kernel/sys_riscv.c > > > +++ b/arch/riscv/kernel/sys_riscv.c > > > @@ -10,6 +10,7 @@ > > > #include <asm/cpufeature.h> > > > #include <asm/hwprobe.h> > > > #include <asm/sbi.h> > > > +#include <asm/vector.h> > > > #include <asm/switch_to.h> > > > #include <asm/uaccess.h> > > > #include <asm/unistd.h> > > > @@ -161,6 +162,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > > > */ > > > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > > > pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; > > > + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_V; > > > > Doesn't this also need a > > if (has_vector()) > > > > If the RISCV_HWPROBE_KEY_BASE_BEHAVIOR part just tells whether hwprobe > supports probing of a set of extensions then I think we should not add > the if statement here, but maybe I misunderstood something.. The intention was to show that the I, M, and A extensions are actually present on this machine, not that the other probe keys exist. Usermode is allowed to query any hwprobe key, they just get back the key set to -1 and value set to 0 on unknown keys. We "cheated" a bit for determining I, M, and A exist since they're already prerequisites of Linux, which is why there's no conditional there. -Evan
On Tue, 09 May 2023 10:32:03 PDT (-0700), Evan Green wrote: > On Tue, May 9, 2023 at 9:41 AM Andy Chiu <andy.chiu@sifive.com> wrote: >> >> On Tue, May 9, 2023 at 7:05 PM Heiko Stübner <heiko@sntech.de> wrote: >> > >> > Am Dienstag, 9. Mai 2023, 12:30:12 CEST schrieb Andy Chiu: >> > > Probing kernel support for Vector extension is available now. >> > > >> > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> >> > > --- >> > > Documentation/riscv/hwprobe.rst | 10 ++++++++++ >> > > arch/riscv/include/asm/hwprobe.h | 2 +- >> > > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ >> > > arch/riscv/kernel/sys_riscv.c | 9 +++++++++ >> > > 4 files changed, 23 insertions(+), 1 deletion(-) >> > > >> > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst >> > > index 9f0dd62dcb5d..b8755e180fbf 100644 >> > > --- a/Documentation/riscv/hwprobe.rst >> > > +++ b/Documentation/riscv/hwprobe.rst >> > > @@ -53,6 +53,9 @@ The following keys are defined: >> > > programs (it may still be executed in userspace via a >> > > kernel-controlled mechanism such as the vDSO). >> > > >> > > + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: Support for Vector extension, as >> > > + defined by verion 1.0 of the RISC-V Vector extension. >> > >> > ^^ version [missing the S] >> > >> > > + >> > > * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions >> > > that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: >> > > base system behavior. >> > > @@ -64,6 +67,13 @@ The following keys are defined: >> > > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined >> > > by version 2.2 of the RISC-V ISA manual. >> > > >> > > +* :c:macro:`RISCV_HWPROBE_KEY_V_EXT_0`: A bitmask containing the extensions >> > > + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: base >> > > + system behavior. >> > > + >> > > + * :c:macro:`RISCV_HWPROBE_V`: The V extension is supported, as defined by >> > > + version 1.0 of the RISC-V Vector extension manual. >> > > + >> > >> > this seems to be doubling the RISCV_HWPROBE_BASE_BEHAVIOR_V state without >> > adding additional information? Both essentially tell the system that >> > V extension "defined by verion 1.0 of the RISC-V Vector extension" is supported. >> >> I was thinking that RISCV_HWPROBE_BASE_BEHAVIOR_V indicates the kernel >> has a probe for vector (just like RISCV_HWPROBE_BASE_BEHAVIOR_IMA) and >> RISCV_HWPROBE_KEY_V_EXT_0 is where the kernel reports what exactly the >> extension is. This maps to the condition matching of F,D, and C in >> IMA. If that is not the case then I think there is no need for this >> entry. >> >> > >> > I don't question that we'll probably need a key for deeper vector- >> > specifics but I guess I'd the commit message should definitly explain >> > why there is a duplication here. >> >> I suppose something like Zvfh should fall into the category of >> RISCV_HWPROBE_KEY_V_EXT_0. I will add this example into the commit >> message if you agree that is a good example. >> >> > >> > >> > > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance >> > > information about the selected set of processors. >> > > >> > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h >> > > index 78936f4ff513..39df8604fea1 100644 >> > > --- a/arch/riscv/include/asm/hwprobe.h >> > > +++ b/arch/riscv/include/asm/hwprobe.h >> > > @@ -8,6 +8,6 @@ >> > > >> > > #include <uapi/asm/hwprobe.h> >> > > >> > > -#define RISCV_HWPROBE_MAX_KEY 5 >> > > +#define RISCV_HWPROBE_MAX_KEY 6 >> > > >> > > #endif >> > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h >> > > index 8d745a4ad8a2..93a7fd3fd341 100644 >> > > --- a/arch/riscv/include/uapi/asm/hwprobe.h >> > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h >> > > @@ -22,6 +22,7 @@ struct riscv_hwprobe { >> > > #define RISCV_HWPROBE_KEY_MIMPID 2 >> > > #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 >> > > #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) >> > > +#define RISCV_HWPROBE_BASE_BEHAVIOR_V (1 << 1) >> > > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 >> > > #define RISCV_HWPROBE_IMA_FD (1 << 0) >> > > #define RISCV_HWPROBE_IMA_C (1 << 1) >> > > @@ -32,6 +33,8 @@ struct riscv_hwprobe { >> > > #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) >> > > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) >> > > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) >> > > +#define RISCV_HWPROBE_KEY_V_EXT_0 6 >> > > +#define RISCV_HWPROBE_V (1 << 0) >> > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ >> > > >> > > #endif >> > > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c >> > > index 5db29683ebee..6280a7f778b3 100644 >> > > --- a/arch/riscv/kernel/sys_riscv.c >> > > +++ b/arch/riscv/kernel/sys_riscv.c >> > > @@ -10,6 +10,7 @@ >> > > #include <asm/cpufeature.h> >> > > #include <asm/hwprobe.h> >> > > #include <asm/sbi.h> >> > > +#include <asm/vector.h> >> > > #include <asm/switch_to.h> >> > > #include <asm/uaccess.h> >> > > #include <asm/unistd.h> >> > > @@ -161,6 +162,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, >> > > */ >> > > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: >> > > pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; >> > > + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_V; >> > >> > Doesn't this also need a >> > if (has_vector()) >> > >> >> If the RISCV_HWPROBE_KEY_BASE_BEHAVIOR part just tells whether hwprobe >> supports probing of a set of extensions then I think we should not add >> the if statement here, but maybe I misunderstood something.. > > The intention was to show that the I, M, and A extensions are actually > present on this machine, not that the other probe keys exist. Usermode > is allowed to query any hwprobe key, they just get back the key set to > -1 and value set to 0 on unknown keys. We "cheated" a bit for > determining I, M, and A exist since they're already prerequisites of > Linux, which is why there's no conditional there. We should probably add a comment so it doesn't trip someone up again. > -Evan
On Tue, May 9, 2023 at 10:59 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Tue, 09 May 2023 10:32:03 PDT (-0700), Evan Green wrote: > > On Tue, May 9, 2023 at 9:41 AM Andy Chiu <andy.chiu@sifive.com> wrote: > >> > >> On Tue, May 9, 2023 at 7:05 PM Heiko Stübner <heiko@sntech.de> wrote: > >> > > >> > Am Dienstag, 9. Mai 2023, 12:30:12 CEST schrieb Andy Chiu: > >> > > Probing kernel support for Vector extension is available now. > >> > > > >> > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > >> > > --- > >> > > Documentation/riscv/hwprobe.rst | 10 ++++++++++ > >> > > arch/riscv/include/asm/hwprobe.h | 2 +- > >> > > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ > >> > > arch/riscv/kernel/sys_riscv.c | 9 +++++++++ > >> > > 4 files changed, 23 insertions(+), 1 deletion(-) > >> > > > >> > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > >> > > index 9f0dd62dcb5d..b8755e180fbf 100644 > >> > > --- a/Documentation/riscv/hwprobe.rst > >> > > +++ b/Documentation/riscv/hwprobe.rst > >> > > @@ -53,6 +53,9 @@ The following keys are defined: > >> > > programs (it may still be executed in userspace via a > >> > > kernel-controlled mechanism such as the vDSO). > >> > > > >> > > + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: Support for Vector extension, as > >> > > + defined by verion 1.0 of the RISC-V Vector extension. > >> > > >> > ^^ version [missing the S] > >> > > >> > > + > >> > > * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions > >> > > that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: > >> > > base system behavior. > >> > > @@ -64,6 +67,13 @@ The following keys are defined: > >> > > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > >> > > by version 2.2 of the RISC-V ISA manual. > >> > > > >> > > +* :c:macro:`RISCV_HWPROBE_KEY_V_EXT_0`: A bitmask containing the extensions > >> > > + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: base > >> > > + system behavior. > >> > > + > >> > > + * :c:macro:`RISCV_HWPROBE_V`: The V extension is supported, as defined by > >> > > + version 1.0 of the RISC-V Vector extension manual. > >> > > + > >> > > >> > this seems to be doubling the RISCV_HWPROBE_BASE_BEHAVIOR_V state without > >> > adding additional information? Both essentially tell the system that > >> > V extension "defined by verion 1.0 of the RISC-V Vector extension" is supported. > >> > >> I was thinking that RISCV_HWPROBE_BASE_BEHAVIOR_V indicates the kernel > >> has a probe for vector (just like RISCV_HWPROBE_BASE_BEHAVIOR_IMA) and > >> RISCV_HWPROBE_KEY_V_EXT_0 is where the kernel reports what exactly the > >> extension is. This maps to the condition matching of F,D, and C in > >> IMA. If that is not the case then I think there is no need for this > >> entry. > >> > >> > > >> > I don't question that we'll probably need a key for deeper vector- > >> > specifics but I guess I'd the commit message should definitly explain > >> > why there is a duplication here. > >> > >> I suppose something like Zvfh should fall into the category of > >> RISCV_HWPROBE_KEY_V_EXT_0. I will add this example into the commit > >> message if you agree that is a good example. > >> > >> > > >> > > >> > > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > >> > > information about the selected set of processors. > >> > > > >> > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > >> > > index 78936f4ff513..39df8604fea1 100644 > >> > > --- a/arch/riscv/include/asm/hwprobe.h > >> > > +++ b/arch/riscv/include/asm/hwprobe.h > >> > > @@ -8,6 +8,6 @@ > >> > > > >> > > #include <uapi/asm/hwprobe.h> > >> > > > >> > > -#define RISCV_HWPROBE_MAX_KEY 5 > >> > > +#define RISCV_HWPROBE_MAX_KEY 6 > >> > > > >> > > #endif > >> > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > >> > > index 8d745a4ad8a2..93a7fd3fd341 100644 > >> > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > >> > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > >> > > @@ -22,6 +22,7 @@ struct riscv_hwprobe { > >> > > #define RISCV_HWPROBE_KEY_MIMPID 2 > >> > > #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 > >> > > #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) > >> > > +#define RISCV_HWPROBE_BASE_BEHAVIOR_V (1 << 1) > >> > > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > >> > > #define RISCV_HWPROBE_IMA_FD (1 << 0) > >> > > #define RISCV_HWPROBE_IMA_C (1 << 1) > >> > > @@ -32,6 +33,8 @@ struct riscv_hwprobe { > >> > > #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) > >> > > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > >> > > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > >> > > +#define RISCV_HWPROBE_KEY_V_EXT_0 6 > >> > > +#define RISCV_HWPROBE_V (1 << 0) > >> > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > >> > > > >> > > #endif > >> > > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > >> > > index 5db29683ebee..6280a7f778b3 100644 > >> > > --- a/arch/riscv/kernel/sys_riscv.c > >> > > +++ b/arch/riscv/kernel/sys_riscv.c > >> > > @@ -10,6 +10,7 @@ > >> > > #include <asm/cpufeature.h> > >> > > #include <asm/hwprobe.h> > >> > > #include <asm/sbi.h> > >> > > +#include <asm/vector.h> > >> > > #include <asm/switch_to.h> > >> > > #include <asm/uaccess.h> > >> > > #include <asm/unistd.h> > >> > > @@ -161,6 +162,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > >> > > */ > >> > > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > >> > > pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; > >> > > + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_V; > >> > > >> > Doesn't this also need a > >> > if (has_vector()) > >> > > >> > >> If the RISCV_HWPROBE_KEY_BASE_BEHAVIOR part just tells whether hwprobe > >> supports probing of a set of extensions then I think we should not add > >> the if statement here, but maybe I misunderstood something.. > > > > The intention was to show that the I, M, and A extensions are actually > > present on this machine, not that the other probe keys exist. Usermode > > is allowed to query any hwprobe key, they just get back the key set to > > -1 and value set to 0 on unknown keys. We "cheated" a bit for > > determining I, M, and A exist since they're already prerequisites of > > Linux, which is why there's no conditional there. > > We should probably add a comment so it doesn't trip someone up again. There is one there, it just got clipped in the context diff. It looks like this (after gmail mangles it): /* * The kernel already assumes that the base single-letter ISA * extensions are supported on all harts, and only supports the * IMA base, so just cheat a bit here and tell that to * userspace. */ case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; break;
On Tue, 09 May 2023 11:29:28 PDT (-0700), Evan Green wrote: > On Tue, May 9, 2023 at 10:59 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: >> >> On Tue, 09 May 2023 10:32:03 PDT (-0700), Evan Green wrote: >> > On Tue, May 9, 2023 at 9:41 AM Andy Chiu <andy.chiu@sifive.com> wrote: >> >> >> >> On Tue, May 9, 2023 at 7:05 PM Heiko Stübner <heiko@sntech.de> wrote: >> >> > >> >> > Am Dienstag, 9. Mai 2023, 12:30:12 CEST schrieb Andy Chiu: >> >> > > Probing kernel support for Vector extension is available now. >> >> > > >> >> > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> >> >> > > --- >> >> > > Documentation/riscv/hwprobe.rst | 10 ++++++++++ >> >> > > arch/riscv/include/asm/hwprobe.h | 2 +- >> >> > > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ >> >> > > arch/riscv/kernel/sys_riscv.c | 9 +++++++++ >> >> > > 4 files changed, 23 insertions(+), 1 deletion(-) >> >> > > >> >> > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst >> >> > > index 9f0dd62dcb5d..b8755e180fbf 100644 >> >> > > --- a/Documentation/riscv/hwprobe.rst >> >> > > +++ b/Documentation/riscv/hwprobe.rst >> >> > > @@ -53,6 +53,9 @@ The following keys are defined: >> >> > > programs (it may still be executed in userspace via a >> >> > > kernel-controlled mechanism such as the vDSO). >> >> > > >> >> > > + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: Support for Vector extension, as >> >> > > + defined by verion 1.0 of the RISC-V Vector extension. >> >> > >> >> > ^^ version [missing the S] >> >> > >> >> > > + >> >> > > * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions >> >> > > that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: >> >> > > base system behavior. >> >> > > @@ -64,6 +67,13 @@ The following keys are defined: >> >> > > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined >> >> > > by version 2.2 of the RISC-V ISA manual. >> >> > > >> >> > > +* :c:macro:`RISCV_HWPROBE_KEY_V_EXT_0`: A bitmask containing the extensions >> >> > > + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: base >> >> > > + system behavior. >> >> > > + >> >> > > + * :c:macro:`RISCV_HWPROBE_V`: The V extension is supported, as defined by >> >> > > + version 1.0 of the RISC-V Vector extension manual. >> >> > > + >> >> > >> >> > this seems to be doubling the RISCV_HWPROBE_BASE_BEHAVIOR_V state without >> >> > adding additional information? Both essentially tell the system that >> >> > V extension "defined by verion 1.0 of the RISC-V Vector extension" is supported. >> >> >> >> I was thinking that RISCV_HWPROBE_BASE_BEHAVIOR_V indicates the kernel >> >> has a probe for vector (just like RISCV_HWPROBE_BASE_BEHAVIOR_IMA) and >> >> RISCV_HWPROBE_KEY_V_EXT_0 is where the kernel reports what exactly the >> >> extension is. This maps to the condition matching of F,D, and C in >> >> IMA. If that is not the case then I think there is no need for this >> >> entry. >> >> >> >> > >> >> > I don't question that we'll probably need a key for deeper vector- >> >> > specifics but I guess I'd the commit message should definitly explain >> >> > why there is a duplication here. >> >> >> >> I suppose something like Zvfh should fall into the category of >> >> RISCV_HWPROBE_KEY_V_EXT_0. I will add this example into the commit >> >> message if you agree that is a good example. >> >> >> >> > >> >> > >> >> > > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance >> >> > > information about the selected set of processors. >> >> > > >> >> > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h >> >> > > index 78936f4ff513..39df8604fea1 100644 >> >> > > --- a/arch/riscv/include/asm/hwprobe.h >> >> > > +++ b/arch/riscv/include/asm/hwprobe.h >> >> > > @@ -8,6 +8,6 @@ >> >> > > >> >> > > #include <uapi/asm/hwprobe.h> >> >> > > >> >> > > -#define RISCV_HWPROBE_MAX_KEY 5 >> >> > > +#define RISCV_HWPROBE_MAX_KEY 6 >> >> > > >> >> > > #endif >> >> > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h >> >> > > index 8d745a4ad8a2..93a7fd3fd341 100644 >> >> > > --- a/arch/riscv/include/uapi/asm/hwprobe.h >> >> > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h >> >> > > @@ -22,6 +22,7 @@ struct riscv_hwprobe { >> >> > > #define RISCV_HWPROBE_KEY_MIMPID 2 >> >> > > #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 >> >> > > #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) >> >> > > +#define RISCV_HWPROBE_BASE_BEHAVIOR_V (1 << 1) V isn't a new base, it's just an addon to IMA like FD and C are. So this should just be another bit in the RISCV_HWPROBE_KEY_IMA_EXT_0 bitset. That'll also clear up the above about V being indicated twice. >> >> > > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 >> >> > > #define RISCV_HWPROBE_IMA_FD (1 << 0) >> >> > > #define RISCV_HWPROBE_IMA_C (1 << 1) >> >> > > @@ -32,6 +33,8 @@ struct riscv_hwprobe { >> >> > > #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) >> >> > > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) >> >> > > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) >> >> > > +#define RISCV_HWPROBE_KEY_V_EXT_0 6 >> >> > > +#define RISCV_HWPROBE_V (1 << 0) >> >> > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ >> >> > > >> >> > > #endif >> >> > > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c >> >> > > index 5db29683ebee..6280a7f778b3 100644 >> >> > > --- a/arch/riscv/kernel/sys_riscv.c >> >> > > +++ b/arch/riscv/kernel/sys_riscv.c >> >> > > @@ -10,6 +10,7 @@ >> >> > > #include <asm/cpufeature.h> >> >> > > #include <asm/hwprobe.h> >> >> > > #include <asm/sbi.h> >> >> > > +#include <asm/vector.h> >> >> > > #include <asm/switch_to.h> >> >> > > #include <asm/uaccess.h> >> >> > > #include <asm/unistd.h> >> >> > > @@ -161,6 +162,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, >> >> > > */ >> >> > > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: >> >> > > pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; >> >> > > + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_V; >> >> > >> >> > Doesn't this also need a >> >> > if (has_vector()) >> >> > >> >> >> >> If the RISCV_HWPROBE_KEY_BASE_BEHAVIOR part just tells whether hwprobe >> >> supports probing of a set of extensions then I think we should not add >> >> the if statement here, but maybe I misunderstood something.. >> > >> > The intention was to show that the I, M, and A extensions are actually >> > present on this machine, not that the other probe keys exist. Usermode >> > is allowed to query any hwprobe key, they just get back the key set to >> > -1 and value set to 0 on unknown keys. We "cheated" a bit for >> > determining I, M, and A exist since they're already prerequisites of >> > Linux, which is why there's no conditional there. >> >> We should probably add a comment so it doesn't trip someone up again. > > There is one there, it just got clipped in the context diff. It looks > like this (after gmail mangles it): > > /* > * The kernel already assumes that the base single-letter ISA > * extensions are supported on all harts, and only supports the > * IMA base, so just cheat a bit here and tell that to > * userspace. > */ > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; > break; OK, not sure how to make that much clearer.
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 9f0dd62dcb5d..b8755e180fbf 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -53,6 +53,9 @@ The following keys are defined: programs (it may still be executed in userspace via a kernel-controlled mechanism such as the vDSO). + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: Support for Vector extension, as + defined by verion 1.0 of the RISC-V Vector extension. + * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. @@ -64,6 +67,13 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. +* :c:macro:`RISCV_HWPROBE_KEY_V_EXT_0`: A bitmask containing the extensions + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_V`: base + system behavior. + + * :c:macro:`RISCV_HWPROBE_V`: The V extension is supported, as defined by + version 1.0 of the RISC-V Vector extension manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 78936f4ff513..39df8604fea1 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include <uapi/asm/hwprobe.h> -#define RISCV_HWPROBE_MAX_KEY 5 +#define RISCV_HWPROBE_MAX_KEY 6 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 8d745a4ad8a2..93a7fd3fd341 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -22,6 +22,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_MIMPID 2 #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_BASE_BEHAVIOR_V (1 << 1) #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) @@ -32,6 +33,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) +#define RISCV_HWPROBE_KEY_V_EXT_0 6 +#define RISCV_HWPROBE_V (1 << 0) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5db29683ebee..6280a7f778b3 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -10,6 +10,7 @@ #include <asm/cpufeature.h> #include <asm/hwprobe.h> #include <asm/sbi.h> +#include <asm/vector.h> #include <asm/switch_to.h> #include <asm/uaccess.h> #include <asm/unistd.h> @@ -161,6 +162,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, */ case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_V; break; case RISCV_HWPROBE_KEY_IMA_EXT_0: @@ -173,6 +175,13 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, break; + case RISCV_HWPROBE_KEY_V_EXT_0: + pair->value = 0; + if (has_vector()) + pair->value |= RISCV_HWPROBE_V; + + break; + case RISCV_HWPROBE_KEY_CPUPERF_0: pair->value = hwprobe_misaligned(cpus); break;
Probing kernel support for Vector extension is available now. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- Documentation/riscv/hwprobe.rst | 10 ++++++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ arch/riscv/kernel/sys_riscv.c | 9 +++++++++ 4 files changed, 23 insertions(+), 1 deletion(-)