| Message ID | 20230510153228.264954-4-shorne@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | OpenRISC updates for user space FPU | expand |
On 5/10/23 16:32, Stafford Horne wrote: > OpenRISC defines tininess to be detected before rounding. Setup qemu to > obey this. > > Signed-off-by: Stafford Horne <shorne@gmail.com> > --- > Since v1: > - Remove setting default NaN behavior. I discussed with the FPU developers and > they mentioned the OpenRISC hardware should be IEEE compliant when handling > and forwarding NaN payloads, and they don't want try change this. There is no such thing as IEEE compliant for NaN payloads. All of that is implementation defined. All OpenRISC needs to do is document its intentions (and then double-check that fpu/softfloat-specialize.c.inc does what is documented). Anyway, back to this patch, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> :-) r~
On Wed, May 10, 2023 at 05:16:20PM +0100, Richard Henderson wrote: > On 5/10/23 16:32, Stafford Horne wrote: > > OpenRISC defines tininess to be detected before rounding. Setup qemu to > > obey this. > > > > Signed-off-by: Stafford Horne <shorne@gmail.com> > > --- > > Since v1: > > - Remove setting default NaN behavior. I discussed with the FPU developers and > > they mentioned the OpenRISC hardware should be IEEE compliant when handling > > and forwarding NaN payloads, and they don't want try change this. > > There is no such thing as IEEE compliant for NaN payloads. > All of that is implementation defined. I see, I haven't yet seen to IEEE 754 spec so I don't know how much is covered. It was incorrect to assume forwarding semantics was covered. > All OpenRISC needs to do is document its intentions (and then double-check > that fpu/softfloat-specialize.c.inc does what is documented). Understood, that makes sense, also reading that code I see how all other architectures are able to ifdef their way to a specific behavior. I will see what our current implementions do and update the spec and qemu as a separate task. > > Anyway, back to this patch, > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > :-) Thank you ^_^ -Stafford
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 0ce4f796fa..61d748cfdc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -22,6 +22,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) @@ -90,6 +91,9 @@ static void openrisc_cpu_reset_hold(Object *obj) s->exception_index = -1; cpu_set_fpcsr(&cpu->env, 0); + set_float_detect_tininess(float_tininess_before_rounding, + &cpu->env.fp_status); + #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; cpu->env.picsr = 0x00000000;
OpenRISC defines tininess to be detected before rounding. Setup qemu to obey this. Signed-off-by: Stafford Horne <shorne@gmail.com> --- Since v1: - Remove setting default NaN behavior. I discussed with the FPU developers and they mentioned the OpenRISC hardware should be IEEE compliant when handling and forwarding NaN payloads, and they don't want try change this. target/openrisc/cpu.c | 4 ++++ 1 file changed, 4 insertions(+)