| Message ID | 20230509151723.84989-3-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Add watchdog nodes in StarFive JH7100/JH7110 DTS | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD ac9a78681b92 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 16 lines checked |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Tue, May 09, 2023 at 11:17:23PM +0800, Xingyu Wu wrote: > Add the watchdog node for the Starfive JH7110 SoC. Emil or Walker, could I get a review on this please? It's the only dts patch on the list right now for the jh7110 that I can actually apply, so it'd be nice to do so. Thanks, Conor. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 4c5fdb905da8..47c163ec0bf1 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -469,6 +469,16 @@ sysgpio: pinctrl@13040000 { > #gpio-cells = <2>; > }; > > + watchdog@13070000 { > + compatible = "starfive,jh7110-wdt"; > + reg = <0x0 0x13070000 0x0 0x10000>; > + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, > + <&syscrg JH7110_SYSCLK_WDT_CORE>; > + clock-names = "apb", "core"; > + resets = <&syscrg JH7110_SYSRST_WDT_APB>, > + <&syscrg JH7110_SYSRST_WDT_CORE>; > + }; > + > aoncrg: clock-controller@17000000 { > compatible = "starfive,jh7110-aoncrg"; > reg = <0x0 0x17000000 0x0 0x10000>; > -- > 2.25.1 >
On 2023/5/13 6:27, Conor Dooley wrote: > On Tue, May 09, 2023 at 11:17:23PM +0800, Xingyu Wu wrote: >> Add the watchdog node for the Starfive JH7110 SoC. > > Emil or Walker, could I get a review on this please? > It's the only dts patch on the list right now for the jh7110 that I can > actually apply, so it'd be nice to do so. Of course, thank you for helping to review and apply. Best regards, Walker
On Mon, May 15, 2023 at 09:47:44AM +0800, Walker Chen wrote: > > > On 2023/5/13 6:27, Conor Dooley wrote: > > On Tue, May 09, 2023 at 11:17:23PM +0800, Xingyu Wu wrote: > >> Add the watchdog node for the Starfive JH7110 SoC. > > > > Emil or Walker, could I get a review on this please? > > It's the only dts patch on the list right now for the jh7110 that I can > > actually apply, so it'd be nice to do so. > > Of course, thank you for helping to review and apply. I was hoping that you would reply with a "Reviewed-by", your thanks is nice to but I can't do anything with that! Cheers, Conor.
On 2023/5/9 23:17, Xingyu Wu wrote: > Add the watchdog node for the Starfive JH7110 SoC. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 4c5fdb905da8..47c163ec0bf1 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -469,6 +469,16 @@ sysgpio: pinctrl@13040000 { > #gpio-cells = <2>; > }; > > + watchdog@13070000 { > + compatible = "starfive,jh7110-wdt"; > + reg = <0x0 0x13070000 0x0 0x10000>; > + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, > + <&syscrg JH7110_SYSCLK_WDT_CORE>; > + clock-names = "apb", "core"; > + resets = <&syscrg JH7110_SYSRST_WDT_APB>, > + <&syscrg JH7110_SYSRST_WDT_CORE>; > + }; > + > aoncrg: clock-controller@17000000 { > compatible = "starfive,jh7110-aoncrg"; > reg = <0x0 0x17000000 0x0 0x10000>; Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Thanks!
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..47c163ec0bf1 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -469,6 +469,16 @@ sysgpio: pinctrl@13040000 { #gpio-cells = <2>; }; + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x0 0x17000000 0x0 0x10000>;
Add the watchdog node for the Starfive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)