| Message ID | IA1PR20MB49539A0A6FEB114B82A2187DBB7E9@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [V2] perf vendor events riscv: add T-HEAD C9xx JSON file | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD ac9a78681b92 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 14 this patch: 14 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 28 this patch: 28 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
> Please put change log and example between > --- > --- > > So it will look like: > > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > > --- > ----> changelog here > ----> example here > > --- > > tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + > > Otherwise it's too verbose and contains stuff related to OpenSBI and > not the perf itself. > > Also checkpatch show some minor problems. > > Also i think a mentioning c906,c910,c920 in commit message and > providing a brief information about their difference. Will fix in V3 > > event id range | support cpu > > 0x01 - 0x06 | c906,c910,c920 > > 0x07 | c906 > > I don't see it in the json file. 0x01 - 0x05 are in cache.json 0x06 - 0x07 should in instruction.json I will fix the left 0x07 and its name in the V3. > > 0x08 - 0x0a | c910,c920 > > 0x0b - 0x0f | c906,c910,c920 > > 0x10 - 0x1a | c910,c920 > > 0x1b - 0x1c | c910,c920 (software defined, >= 0x1b) > > 0x1d - 0x2a | c906 > > So is this a complete list for c906 ? This is a complete list for the whole T-HEAD c9xx series until now. Some of the events can be used in c906 (the line has c906 in the table). > I ll test it soon then, however: > > 1) What version of OpenSBI is used ? > 2) What platforms have you tested ? The mainline OpenSBI is just OK. I have test this on a sophgo sg2042 board (c920). This pmu node is just fine for both c910 and c920. But c906 should change some events as it does not support.
Hi Inochi Amaoto! Please put change log and example between --- --- So it will look like: > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- ----> changelog here ----> example here > --- > tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + Otherwise it's too verbose and contains stuff related to OpenSBI and not the perf itself. Also checkpatch show some minor problems. Also i think a mentioning c906,c910,c920 in commit message and providing a brief information about their difference. > event id range | support cpu > 0x01 - 0x06 | c906,c910,c920 > 0x07 | c906 I don't see it in the json file. > 0x08 - 0x0a | c910,c920 > 0x0b - 0x0f | c906,c910,c920 > 0x10 - 0x1a | c910,c920 > 0x1b - 0x1c | c910,c920 (software defined, >= 0x1b) > 0x1d - 0x2a | c906 So is this a complete list for c906 ? I ll test it soon then, however: 1) What version of OpenSBI is used ? 2) What platforms have you tested ? On Wed, 2023-05-17 at 13:17 +0800, Inochi Amaoto wrote: > Add json file of T-HEAD C9xx events. > > A minimal hpm dtb node example for C910 is as follows, > > pmu { > compatible = "riscv,pmu"; > riscv,event-to-mhpmcounters = > // event-start event-end a bitmap of all the > MHPMCOUNTERx > <0x00006 0x00006 0x00000400>, > <0x00005 0x00005 0x00000800>, > <0x10000 0x10000 0x00004000>, > <0x10001 0x10001 0x00008000>, > <0x10002 0x10002 0x00010000>, > <0x10003 0x10003 0x00020000>, > <0x10008 0x10008 0x00000008>, > <0x10009 0x10009 0x00000010>, > <0x10010 0x10010 0x00040000>, > <0x10011 0x10011 0x00080000>, > <0x10012 0x10012 0x00100000>, > <0x10013 0x10013 0x00200000>, > <0x10019 0x10019 0x00000040>, > <0x10021 0x10021 0x00000020>; > riscv,event-to-mhpmevent = > // event-id event-selector > /* mhpmevent3: L1I_READ_ACCESS */ > <0x10008 0x00000000 0x00000001>, > /* mhpmevent4: L1I_READ_MISS */ > <0x10009 0x00000000 0x00000002>, > /* mhpmevent5: ITLB_READ_MISS */ > <0x10021 0x00000000 0x00000003>, > /* mhpmevent6: DTLB_READ_MISS */ > <0x10019 0x00000000 0x00000004>, > /* mhpmevent10: PMU_HW_BRANCH_MISSES */ > <0x00006 0x00000000 0x00000008>, > /* mhpmevent11: PMU_HW_BRANCH_INSTRUCTIONS */ > <0x00005 0x00000000 0x00000009>, > /* mhpmevent14: L1D_READ_ACCESS */ > <0x10000 0x00000000 0x0000000c>, > /* mhpmevent15: L1D_READ_MISS */ > <0x10001 0x00000000 0x0000000d>, > /* mhpmevent16: L1D_WRITE_ACCESS */ > <0x10002 0x00000000 0x0000000e>, > /* mhpmevent17: L1D_WRITE_MISS */ > <0x10003 0x00000000 0x0000000f>, > /* mhpmevent18: LL_READ_ACCESS */ > <0x10010 0x00000000 0x00000010>, > /* mhpmevent19: LL_READ_MISS */ > <0x10011 0x00000000 0x00000011>, > /* mhpmevent20: LL_WRITE_ACCESS */ > <0x10012 0x00000000 0x00000012>, > /* mhpmevent21: LL_WRITE_MISS */ > <0x10013 0x00000000 0x00000013>; > riscv,raw-event-to-mhpmcounters = > /* mhpmevent3: L1 ICache Access Counter */ > <0x00000000 0x00000001 0xffffffff 0xffffffff > 0x00000008>, > /* mhpmevent4: L1 ICache Miss Counter */ > <0x00000000 0x00000002 0xffffffff 0xffffffff > 0x00000010>, > /* mhpmevent5: I-UTLB Miss Counter */ > <0x00000000 0x00000003 0xffffffff 0xffffffff > 0x00000020>, > /* mhpmevent6: D-UTLB Miss Counter */ > <0x00000000 0x00000004 0xffffffff 0xffffffff > 0x00000040>, > /* mhpmevent7: JTLB Miss */ > <0x00000000 0x00000005 0xffffffff 0xffffffff > 0x00000080>, > /* mhpmevent8: Conditional Branch Mispredict */ > <0x00000000 0x00000006 0xffffffff 0xffffffff > 0x00000100>, > /* mhpmevent9: Conditional Branch Instruction Counter > (reserved for c910)*/ > /* <0x00000000 0x00000007 0xffffffff 0xffffffff > 0x00000200>, */ > /* mhpmevent10: Indirect Branch Mispredict Counter */ > <0x00000000 0x00000008 0xffffffff 0xffffffff > 0x00000400>, > /* mhpmevent11: Indirect Branch Instruction Counter > */ > <0x00000000 0x00000009 0xffffffff 0xffffffff > 0x00000800>, > /* mhpmevent12: LSU Spec Fail */ > <0x00000000 0x0000000a 0xffffffff 0xffffffff > 0x00001000>, > /* mhpmevent13: Store Instruction */ > <0x00000000 0x0000000b 0xffffffff 0xffffffff > 0x00002000>, > /* mhpmevent14: L1 DCache read access Counter */ > <0x00000000 0x0000000c 0xffffffff 0xffffffff > 0x00004000>, > /* mhpmevent15: L1 DCache read miss Counter */ > <0x00000000 0x0000000d 0xffffffff 0xffffffff > 0x00008000>, > /* mhpmevent16: L1 DCache write access Counter */ > <0x00000000 0x0000000e 0xffffffff 0xffffffff > 0x00010000>, > /* mhpmevent17: L1 DCache write access Counter */ > <0x00000000 0x0000000f 0xffffffff 0xffffffff > 0x00020000>, > /* mhpmevent18: L2 Cache read access Counter */ > <0x00000000 0x00000010 0xffffffff 0xffffffff > 0x00040000>, > /* mhpmevent19: L2 Cache read miss Counter */ > <0x00000000 0x00000011 0xffffffff 0xffffffff > 0x00080000>, > /* mhpmevent20: L2 Cache write access Counter */ > <0x00000000 0x00000012 0xffffffff 0xffffffff > 0x00100000>, > /* mhpmevent21: L2 Cache write miss Counter */ > <0x00000000 0x00000013 0xffffffff 0xffffffff > 0x00200000>, > /* mhpmevent22: RF Launch Fail */ > <0x00000000 0x00000014 0xffffffff 0xffffffff > 0x00400000>, > /* mhpmevent23: RF Reg Launch Fail */ > <0x00000000 0x00000015 0xffffffff 0xffffffff > 0x00800000>, > /* mhpmevent24: RF Instruction */ > <0x00000000 0x00000016 0xffffffff 0xffffffff > 0x01000000>, > /* mhpmevent25: LSU Cross 4K Stall */ > <0x00000000 0x00000017 0xffffffff 0xffffffff > 0x02000000>, > /* mhpmevent26: LSU Other Stall */ > <0x00000000 0x00000018 0xffffffff 0xffffffff > 0x04000000>, > /* mhpmevent27: LSU SQ Discard */ > <0x00000000 0x00000019 0xffffffff 0xffffffff > 0x08000000>, > /* mhpmevent28: LSU SQ Data Discard */ > <0x00000000 0x0000001a 0xffffffff 0xffffffff > 0x10000000>; > }; > > Change from v1: > 1. drop patch for checking MARCH and MIMP CSR. > 2. add C906 events to the total json file > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + > .../arch/riscv/t-head/c9xx/cache.json | 67 > ++++++++++++++++++ > .../arch/riscv/t-head/c9xx/firmware.json | 68 > +++++++++++++++++++ > .../arch/riscv/t-head/c9xx/instruction.json | 67 > ++++++++++++++++++ > .../arch/riscv/t-head/c9xx/microarch.json | 67 > ++++++++++++++++++ > 5 files changed, 270 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/riscv/t- > head/c9xx/cache.json > create mode 100644 tools/perf/pmu-events/arch/riscv/t- > head/c9xx/firmware.json > create mode 100644 tools/perf/pmu-events/arch/riscv/t- > head/c9xx/instruction.json > create mode 100644 tools/perf/pmu-events/arch/riscv/t- > head/c9xx/microarch.json > > diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv > b/tools/perf/pmu-events/arch/riscv/mapfile.csv > index c61b3d6ef616..dd1d998a7ad6 100644 > --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv > +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv > @@ -15,3 +15,4 @@ > # > #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType > 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core > +0x5b7-0x0-0x0,v1,t-head/c9xx,core > diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json > b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json > new file mode 100644 > index 000000000000..2c6e9a904a11 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json > @@ -0,0 +1,67 @@ > +[ > + { > + "EventName": "L1_ICACHE_ACCESS", > + "EventCode": "0x000001", > + "BriefDescription": "L1 instruction cache access" > + }, > + { > + "EventName": "L1_ICACHE_MISS", > + "EventCode": "0x000002", > + "BriefDescription": "L1 instruction cache miss" > + }, > + { > + "EventName": "INST_TLB_MISS", > + "EventCode": "0x000003", > + "BriefDescription": "Instruction TLB (I-UTLB) miss" > + }, > + { > + "EventName": "DATA_TLB_MISS", > + "EventCode": "0x000004", > + "BriefDescription": "Data TLB (D-UTLB) miss" > + }, > + { > + "EventName": "JTLB_MISS", > + "EventCode": "0x000005", > + "BriefDescription": "JTLB access miss" > + }, > + { > + "EventName": "L1_DCACHE_READ_ACCESS", > + "EventCode": "0x00000c", > + "BriefDescription": "L1 data cache read access" > + }, > + { > + "EventName": "L1_DCACHE_READ_MISS", > + "EventCode": "0x00000d", > + "BriefDescription": "L1 data cache read miss" > + }, > + { > + "EventName": "L1_DCACHE_WRITE_ACCESS", > + "EventCode": "0x00000e", > + "BriefDescription": "L1 data cache write access" > + }, > + { > + "EventName": "L1_DCACHE_WRITE_MISS", > + "EventCode": "0x00000f", > + "BriefDescription": "L1 data cache write miss" > + }, > + { > + "EventName": "L2_CACHE_READ_ACCESS", > + "EventCode": "0x000010", > + "BriefDescription": "L2 cache read access" > + }, > + { > + "EventName": "L2_CACHE_READ_MISS", > + "EventCode": "0x000011", > + "BriefDescription": "L2 cache read miss" > + }, > + { > + "EventName": "L2_CACHE_WRITE_ACCESS", > + "EventCode": "0x000012", > + "BriefDescription": "L2 cache write access" > + }, > + { > + "EventName": "L2_CACHE_WRITE_MISS", > + "EventCode": "0x000013", > + "BriefDescription": "L2 cache write miss" > + } > +] > diff --git a/tools/perf/pmu-events/arch/riscv/t- > head/c9xx/firmware.json b/tools/perf/pmu-events/arch/riscv/t- > head/c9xx/firmware.json > new file mode 100644 > index 000000000000..9b4a032186a7 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json > @@ -0,0 +1,68 @@ > +[ > + { > + "ArchStdEvent": "FW_MISALIGNED_LOAD" > + }, > + { > + "ArchStdEvent": "FW_MISALIGNED_STORE" > + }, > + { > + "ArchStdEvent": "FW_ACCESS_LOAD" > + }, > + { > + "ArchStdEvent": "FW_ACCESS_STORE" > + }, > + { > + "ArchStdEvent": "FW_ILLEGAL_INSN" > + }, > + { > + "ArchStdEvent": "FW_SET_TIMER" > + }, > + { > + "ArchStdEvent": "FW_IPI_SENT" > + }, > + { > + "ArchStdEvent": "FW_IPI_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_FENCE_I_SENT" > + }, > + { > + "ArchStdEvent": "FW_FENCE_I_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_SFENCE_VMA_SENT" > + }, > + { > + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_GVMA_SENT" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_VVMA_SENT" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT" > + }, > + { > + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED" > + } > +] > diff --git a/tools/perf/pmu-events/arch/riscv/t- > head/c9xx/instruction.json b/tools/perf/pmu-events/arch/riscv/t- > head/c9xx/instruction.json > new file mode 100644 > index 000000000000..7cd064e70c82 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json > @@ -0,0 +1,67 @@ > +[ > + { > + "EventName": "BR_COND_MIS_PRED", > + "EventCode": "0x000006", > + "BriefDescription": "Conditional branch mispredict" > + }, > + { > + "EventName": "BR_INDIRECT_MIS_PRED", > + "EventCode": "0x000008", > + "BriefDescription": "Indirect branch mispredict" > + }, > + { > + "EventName": "BR_INDIRECT_INST", > + "EventCode": "0x000009", > + "BriefDescription": "Indirect branch instruction" > + }, > + { > + "EventName": "INST_STORE", > + "EventCode": "0x00000b", > + "BriefDescription": "Store instruction retired" > + }, > + { > + "EventName": "INST_ALU", > + "EventCode": "0x00001d", > + "BriefDescription": "ALU instruction retired" > + }, > + { > + "EventName": "INST_LOAD_SAVE", > + "EventCode": "0x00001e", > + "BriefDescription": "LOAD/Store instruction retired" > + }, > + { > + "EventName": "INST_VECTOR", > + "EventCode": "0x00001f", > + "BriefDescription": "Vector instruction retired" > + }, > + { > + "EventName": "INST_CSR_ACCESS", > + "EventCode": "0x000020", > + "BriefDescription": "CSR access instruction retired" > + }, > + { > + "EventName": "INST_SYNC", > + "EventCode": "0x000021", > + "BriefDescription": "Sync instruction retired" > + }, > + { > + "EventName": "INST_LOAD_SAVE_UNALIGNED", > + "EventCode": "0x000022", > + "BriefDescription": "Load/Store unaligned access instruction > retired" > + }, > + { > + "EventName": "INST_ENV_CALL", > + "EventCode": "0x000025", > + "BriefDescription": "Environment call instruction retired" > + }, > + { > + "EventName": "INST_LONGJUMP", > + "EventCode": "0x000026", > + "BriefDescription": "Long jump instruction retired (jump dist > over 8MB)" > + }, > + { > + "EventName": "INST_FP", > + "EventCode": "0x00002a", > + "BriefDescription": "Float point instruction retired" > + } > +] > diff --git a/tools/perf/pmu-events/arch/riscv/t- > head/c9xx/microarch.json b/tools/perf/pmu-events/arch/riscv/t- > head/c9xx/microarch.json > new file mode 100644 > index 000000000000..073c1d085021 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json > @@ -0,0 +1,67 @@ > +[ > + { > + "EventName": "LSU_SPEC_FAIL", > + "EventCode": "0x00000a", > + "BriefDescription": "LSU Spec Fail" > + }, > + { > + "EventName": "RF_LAUNCH_FAIL", > + "EventCode": "0x000014", > + "BriefDescription": "Register file launch fail" > + }, > + { > + "EventName": "RF_REG_LAUNCH", > + "EventCode": "0x000015", > + "BriefDescription": "Register file reg launch" > + }, > + { > + "EventName": "RF_INSTRUCTION", > + "EventCode": "0x000016", > + "BriefDescription": "Register file instruction" > + }, > + { > + "EventName": "LSU_STALL_CROSS_4K", > + "EventCode": "0x000017", > + "BriefDescription": "LSU stall with cross 4K access" > + }, > + { > + "EventName": "LSU_STALL_OTHER", > + "EventCode": "0x000018", > + "BriefDescription": "LSU stall with other events" > + }, > + { > + "EventName": "LSU_SQ_DISCARD", > + "EventCode": "0x000019", > + "BriefDescription": "LSU SQ discard" > + }, > + { > + "EventName": "LSU_SQ_DISCARD_DATA", > + "EventCode": "0x00001a", > + "BriefDescription": "LSU SQ data discard" > + }, > + { > + "EventName": "INT_NUMBER", > + "EventCode": "0x000023", > + "BriefDescription": "Interrupt number respond" > + }, > + { > + "EventName": "INT_OFF_CYCLE", > + "EventCode": "0x000024", > + "BriefDescription": "Off cycle before interrupt arbitrating" > + }, > + { > + "EventName": "STALLED_CYCLE_IFU", > + "EventCode": "0x000027", > + "BriefDescription": "Stall cycles of the instruction fetch unit" > + }, > + { > + "EventName": "STALLED_CYCLE_IDU", > + "EventCode": "0x000028", > + "BriefDescription": "Stall cycles of the instruction decoding > unit and next-level pipeline unit" > + }, > + { > + "EventName": "STALLED_CYCLE_SYNC", > + "EventCode": "0x000029", > + "BriefDescription": "Stalled cycle for sync instructions > (FENCE/FENCE.i/SFENCE/SYNC...)" > + } > +]
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv index c61b3d6ef616..dd1d998a7ad6 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -15,3 +15,4 @@ # #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core +0x5b7-0x0-0x0,v1,t-head/c9xx,core diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json new file mode 100644 index 000000000000..2c6e9a904a11 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json @@ -0,0 +1,67 @@ +[ + { + "EventName": "L1_ICACHE_ACCESS", + "EventCode": "0x000001", + "BriefDescription": "L1 instruction cache access" + }, + { + "EventName": "L1_ICACHE_MISS", + "EventCode": "0x000002", + "BriefDescription": "L1 instruction cache miss" + }, + { + "EventName": "INST_TLB_MISS", + "EventCode": "0x000003", + "BriefDescription": "Instruction TLB (I-UTLB) miss" + }, + { + "EventName": "DATA_TLB_MISS", + "EventCode": "0x000004", + "BriefDescription": "Data TLB (D-UTLB) miss" + }, + { + "EventName": "JTLB_MISS", + "EventCode": "0x000005", + "BriefDescription": "JTLB access miss" + }, + { + "EventName": "L1_DCACHE_READ_ACCESS", + "EventCode": "0x00000c", + "BriefDescription": "L1 data cache read access" + }, + { + "EventName": "L1_DCACHE_READ_MISS", + "EventCode": "0x00000d", + "BriefDescription": "L1 data cache read miss" + }, + { + "EventName": "L1_DCACHE_WRITE_ACCESS", + "EventCode": "0x00000e", + "BriefDescription": "L1 data cache write access" + }, + { + "EventName": "L1_DCACHE_WRITE_MISS", + "EventCode": "0x00000f", + "BriefDescription": "L1 data cache write miss" + }, + { + "EventName": "L2_CACHE_READ_ACCESS", + "EventCode": "0x000010", + "BriefDescription": "L2 cache read access" + }, + { + "EventName": "L2_CACHE_READ_MISS", + "EventCode": "0x000011", + "BriefDescription": "L2 cache read miss" + }, + { + "EventName": "L2_CACHE_WRITE_ACCESS", + "EventCode": "0x000012", + "BriefDescription": "L2 cache write access" + }, + { + "EventName": "L2_CACHE_WRITE_MISS", + "EventCode": "0x000013", + "BriefDescription": "L2 cache write miss" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json new file mode 100644 index 000000000000..9b4a032186a7 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json @@ -0,0 +1,68 @@ +[ + { + "ArchStdEvent": "FW_MISALIGNED_LOAD" + }, + { + "ArchStdEvent": "FW_MISALIGNED_STORE" + }, + { + "ArchStdEvent": "FW_ACCESS_LOAD" + }, + { + "ArchStdEvent": "FW_ACCESS_STORE" + }, + { + "ArchStdEvent": "FW_ILLEGAL_INSN" + }, + { + "ArchStdEvent": "FW_SET_TIMER" + }, + { + "ArchStdEvent": "FW_IPI_SENT" + }, + { + "ArchStdEvent": "FW_IPI_RECEIVED" + }, + { + "ArchStdEvent": "FW_FENCE_I_SENT" + }, + { + "ArchStdEvent": "FW_FENCE_I_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_SENT" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json new file mode 100644 index 000000000000..7cd064e70c82 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json @@ -0,0 +1,67 @@ +[ + { + "EventName": "BR_COND_MIS_PRED", + "EventCode": "0x000006", + "BriefDescription": "Conditional branch mispredict" + }, + { + "EventName": "BR_INDIRECT_MIS_PRED", + "EventCode": "0x000008", + "BriefDescription": "Indirect branch mispredict" + }, + { + "EventName": "BR_INDIRECT_INST", + "EventCode": "0x000009", + "BriefDescription": "Indirect branch instruction" + }, + { + "EventName": "INST_STORE", + "EventCode": "0x00000b", + "BriefDescription": "Store instruction retired" + }, + { + "EventName": "INST_ALU", + "EventCode": "0x00001d", + "BriefDescription": "ALU instruction retired" + }, + { + "EventName": "INST_LOAD_SAVE", + "EventCode": "0x00001e", + "BriefDescription": "LOAD/Store instruction retired" + }, + { + "EventName": "INST_VECTOR", + "EventCode": "0x00001f", + "BriefDescription": "Vector instruction retired" + }, + { + "EventName": "INST_CSR_ACCESS", + "EventCode": "0x000020", + "BriefDescription": "CSR access instruction retired" + }, + { + "EventName": "INST_SYNC", + "EventCode": "0x000021", + "BriefDescription": "Sync instruction retired" + }, + { + "EventName": "INST_LOAD_SAVE_UNALIGNED", + "EventCode": "0x000022", + "BriefDescription": "Load/Store unaligned access instruction retired" + }, + { + "EventName": "INST_ENV_CALL", + "EventCode": "0x000025", + "BriefDescription": "Environment call instruction retired" + }, + { + "EventName": "INST_LONGJUMP", + "EventCode": "0x000026", + "BriefDescription": "Long jump instruction retired (jump dist over 8MB)" + }, + { + "EventName": "INST_FP", + "EventCode": "0x00002a", + "BriefDescription": "Float point instruction retired" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json new file mode 100644 index 000000000000..073c1d085021 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json @@ -0,0 +1,67 @@ +[ + { + "EventName": "LSU_SPEC_FAIL", + "EventCode": "0x00000a", + "BriefDescription": "LSU Spec Fail" + }, + { + "EventName": "RF_LAUNCH_FAIL", + "EventCode": "0x000014", + "BriefDescription": "Register file launch fail" + }, + { + "EventName": "RF_REG_LAUNCH", + "EventCode": "0x000015", + "BriefDescription": "Register file reg launch" + }, + { + "EventName": "RF_INSTRUCTION", + "EventCode": "0x000016", + "BriefDescription": "Register file instruction" + }, + { + "EventName": "LSU_STALL_CROSS_4K", + "EventCode": "0x000017", + "BriefDescription": "LSU stall with cross 4K access" + }, + { + "EventName": "LSU_STALL_OTHER", + "EventCode": "0x000018", + "BriefDescription": "LSU stall with other events" + }, + { + "EventName": "LSU_SQ_DISCARD", + "EventCode": "0x000019", + "BriefDescription": "LSU SQ discard" + }, + { + "EventName": "LSU_SQ_DISCARD_DATA", + "EventCode": "0x00001a", + "BriefDescription": "LSU SQ data discard" + }, + { + "EventName": "INT_NUMBER", + "EventCode": "0x000023", + "BriefDescription": "Interrupt number respond" + }, + { + "EventName": "INT_OFF_CYCLE", + "EventCode": "0x000024", + "BriefDescription": "Off cycle before interrupt arbitrating" + }, + { + "EventName": "STALLED_CYCLE_IFU", + "EventCode": "0x000027", + "BriefDescription": "Stall cycles of the instruction fetch unit" + }, + { + "EventName": "STALLED_CYCLE_IDU", + "EventCode": "0x000028", + "BriefDescription": "Stall cycles of the instruction decoding unit and next-level pipeline unit" + }, + { + "EventName": "STALLED_CYCLE_SYNC", + "EventCode": "0x000029", + "BriefDescription": "Stalled cycle for sync instructions (FENCE/FENCE.i/SFENCE/SYNC...)" + } +]
Add json file of T-HEAD C9xx events. A minimal hpm dtb node example for C910 is as follows, pmu { compatible = "riscv,pmu"; riscv,event-to-mhpmcounters = // event-start event-end a bitmap of all the MHPMCOUNTERx <0x00006 0x00006 0x00000400>, <0x00005 0x00005 0x00000800>, <0x10000 0x10000 0x00004000>, <0x10001 0x10001 0x00008000>, <0x10002 0x10002 0x00010000>, <0x10003 0x10003 0x00020000>, <0x10008 0x10008 0x00000008>, <0x10009 0x10009 0x00000010>, <0x10010 0x10010 0x00040000>, <0x10011 0x10011 0x00080000>, <0x10012 0x10012 0x00100000>, <0x10013 0x10013 0x00200000>, <0x10019 0x10019 0x00000040>, <0x10021 0x10021 0x00000020>; riscv,event-to-mhpmevent = // event-id event-selector /* mhpmevent3: L1I_READ_ACCESS */ <0x10008 0x00000000 0x00000001>, /* mhpmevent4: L1I_READ_MISS */ <0x10009 0x00000000 0x00000002>, /* mhpmevent5: ITLB_READ_MISS */ <0x10021 0x00000000 0x00000003>, /* mhpmevent6: DTLB_READ_MISS */ <0x10019 0x00000000 0x00000004>, /* mhpmevent10: PMU_HW_BRANCH_MISSES */ <0x00006 0x00000000 0x00000008>, /* mhpmevent11: PMU_HW_BRANCH_INSTRUCTIONS */ <0x00005 0x00000000 0x00000009>, /* mhpmevent14: L1D_READ_ACCESS */ <0x10000 0x00000000 0x0000000c>, /* mhpmevent15: L1D_READ_MISS */ <0x10001 0x00000000 0x0000000d>, /* mhpmevent16: L1D_WRITE_ACCESS */ <0x10002 0x00000000 0x0000000e>, /* mhpmevent17: L1D_WRITE_MISS */ <0x10003 0x00000000 0x0000000f>, /* mhpmevent18: LL_READ_ACCESS */ <0x10010 0x00000000 0x00000010>, /* mhpmevent19: LL_READ_MISS */ <0x10011 0x00000000 0x00000011>, /* mhpmevent20: LL_WRITE_ACCESS */ <0x10012 0x00000000 0x00000012>, /* mhpmevent21: LL_WRITE_MISS */ <0x10013 0x00000000 0x00000013>; riscv,raw-event-to-mhpmcounters = /* mhpmevent3: L1 ICache Access Counter */ <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, /* mhpmevent4: L1 ICache Miss Counter */ <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, /* mhpmevent5: I-UTLB Miss Counter */ <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, /* mhpmevent6: D-UTLB Miss Counter */ <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, /* mhpmevent7: JTLB Miss */ <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, /* mhpmevent8: Conditional Branch Mispredict */ <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, /* mhpmevent9: Conditional Branch Instruction Counter (reserved for c910)*/ /* <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, */ /* mhpmevent10: Indirect Branch Mispredict Counter */ <0x00000000 0x00000008 0xffffffff 0xffffffff 0x00000400>, /* mhpmevent11: Indirect Branch Instruction Counter */ <0x00000000 0x00000009 0xffffffff 0xffffffff 0x00000800>, /* mhpmevent12: LSU Spec Fail */ <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x00001000>, /* mhpmevent13: Store Instruction */ <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, /* mhpmevent14: L1 DCache read access Counter */ <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, /* mhpmevent15: L1 DCache read miss Counter */ <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, /* mhpmevent16: L1 DCache write access Counter */ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, /* mhpmevent17: L1 DCache write access Counter */ <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>, /* mhpmevent18: L2 Cache read access Counter */ <0x00000000 0x00000010 0xffffffff 0xffffffff 0x00040000>, /* mhpmevent19: L2 Cache read miss Counter */ <0x00000000 0x00000011 0xffffffff 0xffffffff 0x00080000>, /* mhpmevent20: L2 Cache write access Counter */ <0x00000000 0x00000012 0xffffffff 0xffffffff 0x00100000>, /* mhpmevent21: L2 Cache write miss Counter */ <0x00000000 0x00000013 0xffffffff 0xffffffff 0x00200000>, /* mhpmevent22: RF Launch Fail */ <0x00000000 0x00000014 0xffffffff 0xffffffff 0x00400000>, /* mhpmevent23: RF Reg Launch Fail */ <0x00000000 0x00000015 0xffffffff 0xffffffff 0x00800000>, /* mhpmevent24: RF Instruction */ <0x00000000 0x00000016 0xffffffff 0xffffffff 0x01000000>, /* mhpmevent25: LSU Cross 4K Stall */ <0x00000000 0x00000017 0xffffffff 0xffffffff 0x02000000>, /* mhpmevent26: LSU Other Stall */ <0x00000000 0x00000018 0xffffffff 0xffffffff 0x04000000>, /* mhpmevent27: LSU SQ Discard */ <0x00000000 0x00000019 0xffffffff 0xffffffff 0x08000000>, /* mhpmevent28: LSU SQ Data Discard */ <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x10000000>; }; Change from v1: 1. drop patch for checking MARCH and MIMP CSR. 2. add C906 events to the total json file Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + .../arch/riscv/t-head/c9xx/cache.json | 67 ++++++++++++++++++ .../arch/riscv/t-head/c9xx/firmware.json | 68 +++++++++++++++++++ .../arch/riscv/t-head/c9xx/instruction.json | 67 ++++++++++++++++++ .../arch/riscv/t-head/c9xx/microarch.json | 67 ++++++++++++++++++ 5 files changed, 270 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json