| Message ID | 20230517000740.2102599-7-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: move DSC RC tables to drm_dsc_helper.c | expand |
> > The array of rc_parameters contains a mixture of parameters from DSC 1.1 > and DSC 1.2 standards. Split these tow configuration arrays in preparation to > adding more configuration data. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++++++++++++++++++---- > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +- > include/drm/display/drm_dsc_helper.h | 7 +- > 3 files changed, 129 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c > b/drivers/gpu/drm/display/drm_dsc_helper.c > index acb93d4116e0..f9d01d72c1ff 100644 > --- a/drivers/gpu/drm/display/drm_dsc_helper.c > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c > @@ -325,10 +325,88 @@ struct rc_parameters_data { > #define DSC_BPP(bpp) ((bpp) << 4) > > /* > - * Selected Rate Control Related Parameter Recommended Values > - * from DSC_v1.11 spec & C Model release: DSC_model_20161212 > + * Rate Control Related Parameter Recommended Values from DSC_v1.1 > spec > + prior > + * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf) > + * > + * Cross-checked against C Model releases: DSC_model_20161212 and > + 20210623 > */ > -static const struct rc_parameters_data rc_parameters[] = { > +static const struct rc_parameters_data rc_parameters_pre_scr[] = { > + { > + .bpp = DSC_BPP(8), .bpc = 8, > + { 512, 12, 6144, 3, 12, 11, 11, { > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > + } > + } > + }, > + { > + .bpp = DSC_BPP(8), .bpc = 10, > + { 512, 12, 6144, 7, 16, 15, 15, { > + /* > + * DSC model/pre-SCR-cfg has 8 for > range_max_qp[0], however > + * VESA DSC 1.1 Table E-5 sets it to 4. > + */ > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > + } > + } > + }, > + { > + .bpp = DSC_BPP(8), .bpc = 12, > + { 512, 12, 6144, 11, 20, 19, 19, { > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > + { 21, 23, -12 } > + } > + } > + }, > + { > + .bpp = DSC_BPP(12), .bpc = 8, > + { 341, 15, 2048, 3, 12, 11, 11, { > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > + } > + } > + }, > + { > + .bpp = DSC_BPP(12), .bpc = 10, > + { 341, 15, 2048, 7, 16, 15, 15, { > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > + } > + } > + }, > + { > + .bpp = DSC_BPP(12), .bpc = 12, > + { 341, 15, 2048, 11, 20, 19, 19, { > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > + { 21, 23, -12 } > + } > + } > + }, > + { /* sentinel */ } > +}; > + > +/* > + * Selected Rate Control Related Parameter Recommended Values from DSC > +v1.2, v1.2a, v1.2b and > + * DSC_v1.1_E1 specs. > + * > + * Cross-checked against C Model releases: DSC_model_20161212 and > +20210623 */ static const struct rc_parameters_data > +rc_parameters_1_2_444[] = { > { > .bpp = DSC_BPP(6), .bpc = 8, > { 768, 15, 6144, 3, 13, 11, 11, { > @@ -388,22 +466,18 @@ static const struct rc_parameters_data > rc_parameters[] = { > { 512, 12, 6144, 3, 12, 11, 11, { > { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, > - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 }, > + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 } > } > } > }, > { > .bpp = DSC_BPP(8), .bpc = 10, > { 512, 12, 6144, 7, 16, 15, 15, { > - /* > - * DSC model/pre-SCR-cfg has 8 for > range_max_qp[0], however > - * VESA DSC 1.1 Table E-5 sets it to 4. > - */ > - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, > + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, > { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 }, > + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 } > } > } > }, > @@ -412,9 +486,9 @@ static const struct rc_parameters_data > rc_parameters[] = { > { 512, 12, 6144, 11, 20, 19, 19, { > { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, > { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > - { 21, 23, -12 } > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 }, > + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 }, > + { 20, 21, -12 } > } > } > }, > @@ -498,8 +572,8 @@ static const struct rc_parameters_data > rc_parameters[] = { > { 341, 15, 2048, 3, 12, 11, 11, { > { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, > - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } > + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 }, > + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 } > } > } > }, > @@ -508,8 +582,8 @@ static const struct rc_parameters_data > rc_parameters[] = { > { 341, 15, 2048, 7, 16, 15, 15, { > { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, > { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } > + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 }, > + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 } > } > } > }, > @@ -518,9 +592,9 @@ static const struct rc_parameters_data > rc_parameters[] = { > { 341, 15, 2048, 11, 20, 19, 19, { > { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, > { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, > - { 21, 23, -12 } > + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 }, > + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 }, > + { 18, 19, -12 } > } > } > }, > @@ -602,7 +676,8 @@ static const struct rc_parameters_data > rc_parameters[] = { > { /* sentinel */ } > }; > > -static const struct rc_parameters *get_rc_params(u16 dsc_bpp, > +static const struct rc_parameters *get_rc_params(const struct > rc_parameters_data *rc_parameters, > + u16 dsc_bpp, > u8 bits_per_component) > { > int i; > @@ -622,11 +697,13 @@ static const struct rc_parameters > *get_rc_params(u16 dsc_bpp, > * function. > * > * @vdsc_cfg: DSC Configuration data partially filled by driver > + * @type: operating mode and standard to follow > * > * Return: 0 or -error code in case of an error > */ > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg) > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum > +drm_dsc_params_type type) > { > + const struct rc_parameters_data *data; > const struct rc_parameters *rc_params; > int i; > > @@ -634,7 +711,19 @@ int drm_dsc_setup_rc_params(struct > drm_dsc_config *vdsc_cfg) > !vdsc_cfg->bits_per_component)) > return -EINVAL; > > - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel, > + switch (kind) { Shouldn't this be type now. > + case DRM_DSC_1_2_444: > + data = rc_parameters_1_2_444; > + break; > + case DRM_DSC_1_1_PRE_SCR: > + data = rc_parameters_pre_scr; > + break; > + default: > + return -EINVAL; > + } > + > + rc_params = get_rc_params(data, > + vdsc_cfg->bits_per_pixel, > vdsc_cfg->bits_per_component); > if (!rc_params) > return -EINVAL; > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index d4340b18c18d..bd9116d2cd76 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -226,7 +226,15 @@ int intel_dsc_compute_params(struct > intel_crtc_state *pipe_config) > if (DISPLAY_VER(dev_priv) >= 13) { > calculate_rc_params(vdsc_cfg); > } else { > - ret = drm_dsc_setup_rc_params(vdsc_cfg); > + if ((compressed_bpp == 8 || > + compressed_bpp == 12) && > + (vdsc_cfg->bits_per_component == 8 || > + vdsc_cfg->bits_per_component == 10 || > + vdsc_cfg->bits_per_component == 12)) > + ret = drm_dsc_setup_rc_params(vdsc_cfg, > DRM_DSC_1_1_PRE_SCR); > + else > + ret = drm_dsc_setup_rc_params(vdsc_cfg, > DRM_DSC_1_2_444); > + > if (ret) > return ret; > > diff --git a/include/drm/display/drm_dsc_helper.h > b/include/drm/display/drm_dsc_helper.h > index 1681791f65a5..66eac7276d04 100644 > --- a/include/drm/display/drm_dsc_helper.h > +++ b/include/drm/display/drm_dsc_helper.h > @@ -10,12 +10,17 @@ > > #include <drm/display/drm_dsc.h> > > +enum drm_dsc_params_type { > + DRM_DSC_1_2_444, > + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */ }; > + > void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int > drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set > *pps_sdp, > const struct drm_dsc_config *dsc_cfg); void > drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); -int > drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg); > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum > +drm_dsc_params_type type); > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); > > #endif /* _DRM_DSC_HELPER_H_ */ > -- > 2.39.2
Hi Dmitry,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-intel/for-linux-next-fixes drm-misc/drm-misc-next drm/drm-next linus/master v6.4-rc2 next-20230517]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230517-081003
base: git://anongit.freedesktop.org/drm-intel for-linux-next
patch link: https://lore.kernel.org/r/20230517000740.2102599-7-dmitry.baryshkov%40linaro.org
patch subject: [PATCH v6 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
config: riscv-randconfig-r002-20230517
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project b0fb98227c90adf2536c9ad644a74d5e92961111)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/7aca8a915864e28aaf1bd69ae49adce19f8c9fc3
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230517-081003
git checkout 7aca8a915864e28aaf1bd69ae49adce19f8c9fc3
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202305171648.maFeL0y5-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/display/drm_dsc_helper.c:714:10: error: use of undeclared identifier 'kind'
switch (kind) {
^
1 error generated.
vim +/kind +714 drivers/gpu/drm/display/drm_dsc_helper.c
692
693 /**
694 * drm_dsc_setup_rc_params() - Set parameters and limits for RC model in
695 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
696 * Required bits_per_pixel and bits_per_component to be set before calling this
697 * function.
698 *
699 * @vdsc_cfg: DSC Configuration data partially filled by driver
700 * @type: operating mode and standard to follow
701 *
702 * Return: 0 or -error code in case of an error
703 */
704 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type)
705 {
706 const struct rc_parameters_data *data;
707 const struct rc_parameters *rc_params;
708 int i;
709
710 if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel ||
711 !vdsc_cfg->bits_per_component))
712 return -EINVAL;
713
> 714 switch (kind) {
715 case DRM_DSC_1_2_444:
716 data = rc_parameters_1_2_444;
717 break;
718 case DRM_DSC_1_1_PRE_SCR:
719 data = rc_parameters_pre_scr;
720 break;
721 default:
722 return -EINVAL;
723 }
724
725 rc_params = get_rc_params(data,
726 vdsc_cfg->bits_per_pixel,
727 vdsc_cfg->bits_per_component);
728 if (!rc_params)
729 return -EINVAL;
730
731 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
732 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
733 vdsc_cfg->initial_offset = rc_params->initial_offset;
734 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
735 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
736 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
737 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
738
739 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
740 vdsc_cfg->rc_range_params[i].range_min_qp =
741 rc_params->rc_range_params[i].range_min_qp;
742 vdsc_cfg->rc_range_params[i].range_max_qp =
743 rc_params->rc_range_params[i].range_max_qp;
744 /*
745 * Range BPG Offset uses 2's complement and is only a 6 bits. So
746 * mask it to get only 6 bits.
747 */
748 vdsc_cfg->rc_range_params[i].range_bpg_offset =
749 rc_params->rc_range_params[i].range_bpg_offset &
750 DSC_RANGE_BPG_OFFSET_MASK;
751 }
752
753 return 0;
754 }
755 EXPORT_SYMBOL(drm_dsc_setup_rc_params);
756
Hi Dmitry,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-intel/for-linux-next-fixes drm-misc/drm-misc-next drm/drm-next linus/master v6.4-rc2 next-20230517]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230517-081003
base: git://anongit.freedesktop.org/drm-intel for-linux-next
patch link: https://lore.kernel.org/r/20230517000740.2102599-7-dmitry.baryshkov%40linaro.org
patch subject: [PATCH v6 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
config: x86_64-rhel-8.3
compiler: gcc-11 (Debian 11.3.0-12) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/7aca8a915864e28aaf1bd69ae49adce19f8c9fc3
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230517-081003
git checkout 7aca8a915864e28aaf1bd69ae49adce19f8c9fc3
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=x86_64 olddefconfig
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/display/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202305171615.1Q1fVwDy-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/display/drm_dsc_helper.c: In function 'drm_dsc_setup_rc_params':
>> drivers/gpu/drm/display/drm_dsc_helper.c:714:17: error: 'kind' undeclared (first use in this function)
714 | switch (kind) {
| ^~~~
drivers/gpu/drm/display/drm_dsc_helper.c:714:17: note: each undeclared identifier is reported only once for each function it appears in
vim +/kind +714 drivers/gpu/drm/display/drm_dsc_helper.c
692
693 /**
694 * drm_dsc_setup_rc_params() - Set parameters and limits for RC model in
695 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
696 * Required bits_per_pixel and bits_per_component to be set before calling this
697 * function.
698 *
699 * @vdsc_cfg: DSC Configuration data partially filled by driver
700 * @type: operating mode and standard to follow
701 *
702 * Return: 0 or -error code in case of an error
703 */
704 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type)
705 {
706 const struct rc_parameters_data *data;
707 const struct rc_parameters *rc_params;
708 int i;
709
710 if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel ||
711 !vdsc_cfg->bits_per_component))
712 return -EINVAL;
713
> 714 switch (kind) {
715 case DRM_DSC_1_2_444:
716 data = rc_parameters_1_2_444;
717 break;
718 case DRM_DSC_1_1_PRE_SCR:
719 data = rc_parameters_pre_scr;
720 break;
721 default:
722 return -EINVAL;
723 }
724
725 rc_params = get_rc_params(data,
726 vdsc_cfg->bits_per_pixel,
727 vdsc_cfg->bits_per_component);
728 if (!rc_params)
729 return -EINVAL;
730
731 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
732 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
733 vdsc_cfg->initial_offset = rc_params->initial_offset;
734 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
735 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
736 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
737 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
738
739 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
740 vdsc_cfg->rc_range_params[i].range_min_qp =
741 rc_params->rc_range_params[i].range_min_qp;
742 vdsc_cfg->rc_range_params[i].range_max_qp =
743 rc_params->rc_range_params[i].range_max_qp;
744 /*
745 * Range BPG Offset uses 2's complement and is only a 6 bits. So
746 * mask it to get only 6 bits.
747 */
748 vdsc_cfg->rc_range_params[i].range_bpg_offset =
749 rc_params->rc_range_params[i].range_bpg_offset &
750 DSC_RANGE_BPG_OFFSET_MASK;
751 }
752
753 return 0;
754 }
755 EXPORT_SYMBOL(drm_dsc_setup_rc_params);
756
On 17/05/2023 06:10, Kandpal, Suraj wrote: >> >> The array of rc_parameters contains a mixture of parameters from DSC 1.1 >> and DSC 1.2 standards. Split these tow configuration arrays in preparation to >> adding more configuration data. >> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++++++++++++++++++---- >> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +- >> include/drm/display/drm_dsc_helper.h | 7 +- >> 3 files changed, 129 insertions(+), 27 deletions(-) >> >> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c >> b/drivers/gpu/drm/display/drm_dsc_helper.c >> index acb93d4116e0..f9d01d72c1ff 100644 >> --- a/drivers/gpu/drm/display/drm_dsc_helper.c >> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c >> @@ -325,10 +325,88 @@ struct rc_parameters_data { >> #define DSC_BPP(bpp) ((bpp) << 4) >> >> /* >> - * Selected Rate Control Related Parameter Recommended Values >> - * from DSC_v1.11 spec & C Model release: DSC_model_20161212 >> + * Rate Control Related Parameter Recommended Values from DSC_v1.1 >> spec >> + prior >> + * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf) >> + * >> + * Cross-checked against C Model releases: DSC_model_20161212 and >> + 20210623 >> */ >> -static const struct rc_parameters_data rc_parameters[] = { >> +static const struct rc_parameters_data rc_parameters_pre_scr[] = { >> + { >> + .bpp = DSC_BPP(8), .bpc = 8, >> + { 512, 12, 6144, 3, 12, 11, 11, { >> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, >> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, >> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, >> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } >> + } >> + } >> + }, >> + { >> + .bpp = DSC_BPP(8), .bpc = 10, >> + { 512, 12, 6144, 7, 16, 15, 15, { >> + /* >> + * DSC model/pre-SCR-cfg has 8 for >> range_max_qp[0], however >> + * VESA DSC 1.1 Table E-5 sets it to 4. >> + */ >> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, >> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, >> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, >> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } >> + } >> + } >> + }, >> + { >> + .bpp = DSC_BPP(8), .bpc = 12, >> + { 512, 12, 6144, 11, 20, 19, 19, { >> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, >> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, >> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, >> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, >> + { 21, 23, -12 } >> + } >> + } >> + }, >> + { >> + .bpp = DSC_BPP(12), .bpc = 8, >> + { 341, 15, 2048, 3, 12, 11, 11, { >> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, >> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, >> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, >> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } >> + } >> + } >> + }, >> + { >> + .bpp = DSC_BPP(12), .bpc = 10, >> + { 341, 15, 2048, 7, 16, 15, 15, { >> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, >> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, >> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, >> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } >> + } >> + } >> + }, >> + { >> + .bpp = DSC_BPP(12), .bpc = 12, >> + { 341, 15, 2048, 11, 20, 19, 19, { >> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, >> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, >> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, >> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, >> + { 21, 23, -12 } >> + } >> + } >> + }, >> + { /* sentinel */ } >> +}; >> + >> +/* >> + * Selected Rate Control Related Parameter Recommended Values from DSC >> +v1.2, v1.2a, v1.2b and >> + * DSC_v1.1_E1 specs. >> + * >> + * Cross-checked against C Model releases: DSC_model_20161212 and >> +20210623 */ static const struct rc_parameters_data >> +rc_parameters_1_2_444[] = { >> { >> .bpp = DSC_BPP(6), .bpc = 8, >> { 768, 15, 6144, 3, 13, 11, 11, { >> @@ -388,22 +466,18 @@ static const struct rc_parameters_data >> rc_parameters[] = { >> { 512, 12, 6144, 3, 12, 11, 11, { >> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, >> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, >> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, >> - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } >> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 }, >> + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 } >> } >> } >> }, >> { >> .bpp = DSC_BPP(8), .bpc = 10, >> { 512, 12, 6144, 7, 16, 15, 15, { >> - /* >> - * DSC model/pre-SCR-cfg has 8 for >> range_max_qp[0], however >> - * VESA DSC 1.1 Table E-5 sets it to 4. >> - */ >> - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, >> + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, >> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, >> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, >> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } >> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 }, >> + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 } >> } >> } >> }, >> @@ -412,9 +486,9 @@ static const struct rc_parameters_data >> rc_parameters[] = { >> { 512, 12, 6144, 11, 20, 19, 19, { >> { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, >> { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, >> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, >> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, >> - { 21, 23, -12 } >> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 }, >> + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 }, >> + { 20, 21, -12 } >> } >> } >> }, >> @@ -498,8 +572,8 @@ static const struct rc_parameters_data >> rc_parameters[] = { >> { 341, 15, 2048, 3, 12, 11, 11, { >> { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, >> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, >> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, >> - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } >> + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 }, >> + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 } >> } >> } >> }, >> @@ -508,8 +582,8 @@ static const struct rc_parameters_data >> rc_parameters[] = { >> { 341, 15, 2048, 7, 16, 15, 15, { >> { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, >> { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, >> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, >> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } >> + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 }, >> + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 } >> } >> } >> }, >> @@ -518,9 +592,9 @@ static const struct rc_parameters_data >> rc_parameters[] = { >> { 341, 15, 2048, 11, 20, 19, 19, { >> { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, >> { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, >> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, >> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, >> - { 21, 23, -12 } >> + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 }, >> + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 }, >> + { 18, 19, -12 } >> } >> } >> }, >> @@ -602,7 +676,8 @@ static const struct rc_parameters_data >> rc_parameters[] = { >> { /* sentinel */ } >> }; >> >> -static const struct rc_parameters *get_rc_params(u16 dsc_bpp, >> +static const struct rc_parameters *get_rc_params(const struct >> rc_parameters_data *rc_parameters, >> + u16 dsc_bpp, >> u8 bits_per_component) >> { >> int i; >> @@ -622,11 +697,13 @@ static const struct rc_parameters >> *get_rc_params(u16 dsc_bpp, >> * function. >> * >> * @vdsc_cfg: DSC Configuration data partially filled by driver >> + * @type: operating mode and standard to follow >> * >> * Return: 0 or -error code in case of an error >> */ >> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg) >> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum >> +drm_dsc_params_type type) >> { >> + const struct rc_parameters_data *data; >> const struct rc_parameters *rc_params; >> int i; >> >> @@ -634,7 +711,19 @@ int drm_dsc_setup_rc_params(struct >> drm_dsc_config *vdsc_cfg) >> !vdsc_cfg->bits_per_component)) >> return -EINVAL; >> >> - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel, >> + switch (kind) { > > Shouldn't this be type now. Yes. I missed one hunk when squashing fixup patches. > > >> + case DRM_DSC_1_2_444: >> + data = rc_parameters_1_2_444; >> + break; >> + case DRM_DSC_1_1_PRE_SCR: >> + data = rc_parameters_pre_scr; >> + break; >> + default: >> + return -EINVAL; >> + } >> + >> + rc_params = get_rc_params(data, >> + vdsc_cfg->bits_per_pixel, >> vdsc_cfg->bits_per_component); >> if (!rc_params) >> return -EINVAL; >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c >> b/drivers/gpu/drm/i915/display/intel_vdsc.c >> index d4340b18c18d..bd9116d2cd76 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c >> @@ -226,7 +226,15 @@ int intel_dsc_compute_params(struct >> intel_crtc_state *pipe_config) >> if (DISPLAY_VER(dev_priv) >= 13) { >> calculate_rc_params(vdsc_cfg); >> } else { >> - ret = drm_dsc_setup_rc_params(vdsc_cfg); >> + if ((compressed_bpp == 8 || >> + compressed_bpp == 12) && >> + (vdsc_cfg->bits_per_component == 8 || >> + vdsc_cfg->bits_per_component == 10 || >> + vdsc_cfg->bits_per_component == 12)) >> + ret = drm_dsc_setup_rc_params(vdsc_cfg, >> DRM_DSC_1_1_PRE_SCR); >> + else >> + ret = drm_dsc_setup_rc_params(vdsc_cfg, >> DRM_DSC_1_2_444); >> + >> if (ret) >> return ret; >> >> diff --git a/include/drm/display/drm_dsc_helper.h >> b/include/drm/display/drm_dsc_helper.h >> index 1681791f65a5..66eac7276d04 100644 >> --- a/include/drm/display/drm_dsc_helper.h >> +++ b/include/drm/display/drm_dsc_helper.h >> @@ -10,12 +10,17 @@ >> >> #include <drm/display/drm_dsc.h> >> >> +enum drm_dsc_params_type { >> + DRM_DSC_1_2_444, >> + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */ }; >> + >> void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int >> drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); >> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set >> *pps_sdp, >> const struct drm_dsc_config *dsc_cfg); void >> drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); -int >> drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg); >> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum >> +drm_dsc_params_type type); >> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); >> >> #endif /* _DRM_DSC_HELPER_H_ */ >> -- >> 2.39.2 >
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index acb93d4116e0..f9d01d72c1ff 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -325,10 +325,88 @@ struct rc_parameters_data { #define DSC_BPP(bpp) ((bpp) << 4) /* - * Selected Rate Control Related Parameter Recommended Values - * from DSC_v1.11 spec & C Model release: DSC_model_20161212 + * Rate Control Related Parameter Recommended Values from DSC_v1.1 spec prior + * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf) + * + * Cross-checked against C Model releases: DSC_model_20161212 and 20210623 */ -static const struct rc_parameters_data rc_parameters[] = { +static const struct rc_parameters_data rc_parameters_pre_scr[] = { + { + .bpp = DSC_BPP(8), .bpc = 8, + { 512, 12, 6144, 3, 12, 11, 11, { + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 10, + { 512, 12, 6144, 7, 16, 15, 15, { + /* + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however + * VESA DSC 1.1 Table E-5 sets it to 4. + */ + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + } + } + }, + { + .bpp = DSC_BPP(8), .bpc = 12, + { 512, 12, 6144, 11, 20, 19, 19, { + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, + { 21, 23, -12 } + } + } + }, + { + .bpp = DSC_BPP(12), .bpc = 8, + { 341, 15, 2048, 3, 12, 11, 11, { + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + } + } + }, + { + .bpp = DSC_BPP(12), .bpc = 10, + { 341, 15, 2048, 7, 16, 15, 15, { + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + } + } + }, + { + .bpp = DSC_BPP(12), .bpc = 12, + { 341, 15, 2048, 11, 20, 19, 19, { + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, + { 21, 23, -12 } + } + } + }, + { /* sentinel */ } +}; + +/* + * Selected Rate Control Related Parameter Recommended Values from DSC v1.2, v1.2a, v1.2b and + * DSC_v1.1_E1 specs. + * + * Cross-checked against C Model releases: DSC_model_20161212 and 20210623 + */ +static const struct rc_parameters_data rc_parameters_1_2_444[] = { { .bpp = DSC_BPP(6), .bpc = 8, { 768, 15, 6144, 3, 13, 11, 11, { @@ -388,22 +466,18 @@ static const struct rc_parameters_data rc_parameters[] = { { 512, 12, 6144, 3, 12, 11, 11, { { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 }, + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 } } } }, { .bpp = DSC_BPP(8), .bpc = 10, { 512, 12, 6144, 7, 16, 15, 15, { - /* - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however - * VESA DSC 1.1 Table E-5 sets it to 4. - */ - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 }, + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 } } } }, @@ -412,9 +486,9 @@ static const struct rc_parameters_data rc_parameters[] = { { 512, 12, 6144, 11, 20, 19, 19, { { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, - { 21, 23, -12 } + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 }, + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 }, + { 20, 21, -12 } } } }, @@ -498,8 +572,8 @@ static const struct rc_parameters_data rc_parameters[] = { { 341, 15, 2048, 3, 12, 11, 11, { { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 }, + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 } } } }, @@ -508,8 +582,8 @@ static const struct rc_parameters_data rc_parameters[] = { { 341, 15, 2048, 7, 16, 15, 15, { { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 }, + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 } } } }, @@ -518,9 +592,9 @@ static const struct rc_parameters_data rc_parameters[] = { { 341, 15, 2048, 11, 20, 19, 19, { { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, - { 21, 23, -12 } + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 }, + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 }, + { 18, 19, -12 } } } }, @@ -602,7 +676,8 @@ static const struct rc_parameters_data rc_parameters[] = { { /* sentinel */ } }; -static const struct rc_parameters *get_rc_params(u16 dsc_bpp, +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters, + u16 dsc_bpp, u8 bits_per_component) { int i; @@ -622,11 +697,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp, * function. * * @vdsc_cfg: DSC Configuration data partially filled by driver + * @type: operating mode and standard to follow * * Return: 0 or -error code in case of an error */ -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg) +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type) { + const struct rc_parameters_data *data; const struct rc_parameters *rc_params; int i; @@ -634,7 +711,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg) !vdsc_cfg->bits_per_component)) return -EINVAL; - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel, + switch (kind) { + case DRM_DSC_1_2_444: + data = rc_parameters_1_2_444; + break; + case DRM_DSC_1_1_PRE_SCR: + data = rc_parameters_pre_scr; + break; + default: + return -EINVAL; + } + + rc_params = get_rc_params(data, + vdsc_cfg->bits_per_pixel, vdsc_cfg->bits_per_component); if (!rc_params) return -EINVAL; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index d4340b18c18d..bd9116d2cd76 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -226,7 +226,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) if (DISPLAY_VER(dev_priv) >= 13) { calculate_rc_params(vdsc_cfg); } else { - ret = drm_dsc_setup_rc_params(vdsc_cfg); + if ((compressed_bpp == 8 || + compressed_bpp == 12) && + (vdsc_cfg->bits_per_component == 8 || + vdsc_cfg->bits_per_component == 10 || + vdsc_cfg->bits_per_component == 12)) + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR); + else + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444); + if (ret) return ret; diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index 1681791f65a5..66eac7276d04 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -10,12 +10,17 @@ #include <drm/display/drm_dsc.h> +enum drm_dsc_params_type { + DRM_DSC_1_2_444, + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */ +}; + void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg); +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); #endif /* _DRM_DSC_HELPER_H_ */
The array of rc_parameters contains a mixture of parameters from DSC 1.1 and DSC 1.2 standards. Split these tow configuration arrays in preparation to adding more configuration data. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++++++++++++++++++---- drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +- include/drm/display/drm_dsc_helper.h | 7 +- 3 files changed, 129 insertions(+), 27 deletions(-)