| Message ID | 20230423101112.13803-3-binbin.wu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: Fix some comments | expand |
On Sun, Apr 23, 2023, Binbin Wu wrote: > msrs_to_save_all is out-dated after commit 2374b7310b66 > (KVM: x86/pmu: Use separate array for defining "PMU MSRs to save"). > Update the comments to msrs_to_save_base. > > Fix a typo in x86 mmu.rst. Please split this into two patches, these are two completely unrelated changes. Yes, they're tiny, but the mmu.rst change is more than just a trivial typo, e.g. it can't be reasonably reviewed by someone without at least passing knowledge of NPT, LA57, etc.
On 5/18/2023 5:28 AM, Sean Christopherson wrote: > On Sun, Apr 23, 2023, Binbin Wu wrote: >> msrs_to_save_all is out-dated after commit 2374b7310b66 >> (KVM: x86/pmu: Use separate array for defining "PMU MSRs to save"). >> Update the comments to msrs_to_save_base. >> >> Fix a typo in x86 mmu.rst. > Please split this into two patches, these are two completely unrelated changes. > Yes, they're tiny, but the mmu.rst change is more than just a trivial typo, e.g. > it can't be reasonably reviewed by someone without at least passing knowledge of > NPT, LA57, etc. OK, will split it. Thanks.
diff --git a/Documentation/virt/kvm/x86/mmu.rst b/Documentation/virt/kvm/x86/mmu.rst index 8364afa228ec..26f62034b6f3 100644 --- a/Documentation/virt/kvm/x86/mmu.rst +++ b/Documentation/virt/kvm/x86/mmu.rst @@ -205,7 +205,7 @@ Shadow pages contain the following information: role.passthrough: The page is not backed by a guest page table, but its first entry points to one. This is set if NPT uses 5-level page tables (host - CR4.LA57=1) and is shadowing L1's 4-level NPT (L1 CR4.LA57=1). + CR4.LA57=1) and is shadowing L1's 4-level NPT (L1 CR4.LA57=0). gfn: Either the guest page table containing the translations shadowed by this page, or the base page frame for linear translations. See role.direct. diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 1b74da8682a0..d02150a1c909 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1430,7 +1430,7 @@ EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); * * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) * extract the supported MSRs from the related const lists. - * msrs_to_save is selected from the msrs_to_save_all to reflect the + * msrs_to_save is selected from the msrs_to_save_base to reflect the * capabilities of the host cpu. This capabilities test skips MSRs that are * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs * may depend on host virtualization features rather than host cpu features. @@ -1533,7 +1533,7 @@ static const u32 emulated_msrs_all[] = { * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. * We always support the "true" VMX control MSRs, even if the host * processor does not, so I am putting these registers here rather - * than in msrs_to_save_all. + * than in msrs_to_save_base. */ MSR_IA32_VMX_BASIC, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
msrs_to_save_all is out-dated after commit 2374b7310b66 (KVM: x86/pmu: Use separate array for defining "PMU MSRs to save"). Update the comments to msrs_to_save_base. Fix a typo in x86 mmu.rst. Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com> --- Documentation/virt/kvm/x86/mmu.rst | 2 +- arch/x86/kvm/x86.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)