| Message ID | 20230518161949.11203-24-andy.chiu@sifive.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: Add vector ISA support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD ac9a78681b92 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | fail | Errors and warnings before: 16381 this patch: 16383 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 55 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Thu, May 18, 2023 at 04:19:46PM +0000, Andy Chiu wrote: > From: Guo Ren <guoren@linux.alibaba.com> > > This patch adds configs for building Vector code. First it detects the > reqired toolchain support for building the code. Then it provides an > option setting whether Vector is implicitly enabled to userspace. > > Signed-off-by: Guo Ren <guoren@linux.alibaba.com> > Co-developed-by: Greentime Hu <greentime.hu@sifive.com> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > Suggested-by: Conor Dooley <conor.dooley@microchip.com>> You can drop this tag if you respin, I just provided review comments ;) Also, it has an extra > at the end. Otherwise, I am still not sold on the "default y", but we can always flip it if there is in fact a regression. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks.
On Thu, 18 May 2023 10:31:37 PDT (-0700), Conor Dooley wrote: > On Thu, May 18, 2023 at 04:19:46PM +0000, Andy Chiu wrote: >> From: Guo Ren <guoren@linux.alibaba.com> >> >> This patch adds configs for building Vector code. First it detects the >> reqired toolchain support for building the code. Then it provides an >> option setting whether Vector is implicitly enabled to userspace. >> >> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> >> Co-developed-by: Greentime Hu <greentime.hu@sifive.com> >> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > >> Suggested-by: Conor Dooley <conor.dooley@microchip.com>> > > You can drop this tag if you respin, I just provided review comments ;) > Also, it has an extra > at the end. > > Otherwise, I am still not sold on the "default y", but we can always > flip it if there is in fact a regression. It's definately the riskier of the options, but the uABI issue will only manifest on systems that have V hardware. Those don't exist yet, so aside from folks running QEMU (who probably want V) we're only risking tripping up users on pre-release silicion -- and that's always a headache, so whatever ;) > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Thanks.
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1019b519d590..f3ba0a8b085e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -466,6 +466,37 @@ config RISCV_ISA_SVPBMT If you don't know what to do here, say Y. +config TOOLCHAIN_HAS_V + bool + default y + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64iv) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32iv) + depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800 + depends on AS_HAS_OPTION_ARCH + +config RISCV_ISA_V + bool "VECTOR extension support" + depends on TOOLCHAIN_HAS_V + depends on FPU + select DYNAMIC_SIGFRAME + default y + help + Say N here if you want to disable all vector related procedure + in the kernel. + + If you don't know what to do here, say Y. + +config RISCV_ISA_V_DEFAULT_ENABLE + bool "Enable userspace Vector by default" + depends on RISCV_ISA_V + default y + help + Say Y here if you want to enable Vector in userspace by default. + Otherwise, userspace has to make explicit prctl() call to enable + Vector, or enable it via the sysctl interface. + + If you don't know what to do here, say Y. + config TOOLCHAIN_HAS_ZBB bool default y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0fb256bf8270..6ec6d52a4180 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -60,6 +60,7 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c +riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC KBUILD_CFLAGS += -Wa,-misa-spec=2.2 @@ -71,7 +72,10 @@ endif # Check if the toolchain supports Zihintpause extension riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause -KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) +# Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by +# matching non-v and non-multi-letter extensions out with the filter ([^v_]*) +KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/') + KBUILD_AFLAGS += -march=$(riscv-march-y) KBUILD_CFLAGS += -mno-save-restore