| Message ID | 20230428223646.23595-3-quic_abhinavk@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [v3,1/4] drm/msm/dpu: remove DPU_DSPP_GC handling in dspp flush | expand |
On 2023-04-28 15:36:45, Abhinav Kumar wrote: > Gamma Correction (GC) and Inverse Gamma Correction(IGC) is > currently unused. In addition dpu_dspp_sub_blks didn't even have an igc > member describing the block. > > Drop related code from the dpu hardware catalog otherwise this becomes a > burden to carry across chipsets in the catalog. > > changes in v3: > - drop IGC related code from dpu_hw_catalog too > - update commit text accordingly > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 +--- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 10 ---------- > 2 files changed, 1 insertion(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 5d994bce696f..791a6fc8bdbf 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -91,7 +91,7 @@ > > #define MERGE_3D_SM8150_MASK (0) > > -#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) Oops we weren't even using parenthesis here before... > +#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) > > #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) > > @@ -449,8 +449,6 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { > static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { > .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, > .len = 0x90, .version = 0x10007}, > - .gc = { .id = DPU_DSPP_GC, .base = 0x17c0, > - .len = 0x90, .version = 0x10007}, > }; > > static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 71584cd56fd7..1230739e37d4 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -127,13 +127,9 @@ enum { > /** > * DSPP sub-blocks > * @DPU_DSPP_PCC Panel color correction block > - * @DPU_DSPP_GC Gamma correction block > - * @DPU_DSPP_IGC Inverse gamma correction block > */ > enum { > DPU_DSPP_PCC = 0x1, > - DPU_DSPP_GC, > - DPU_DSPP_IGC, > DPU_DSPP_MAX > }; > > @@ -398,7 +394,6 @@ struct dpu_caps { > * @hsic: > * @memcolor: > * @pcc_blk: > - * @igc_blk: > * @format_list: Pointer to list of supported formats > * @num_formats: Number of supported formats > * @virt_format_list: Pointer to list of supported formats for virtual planes > @@ -419,7 +414,6 @@ struct dpu_sspp_sub_blks { > struct dpu_pp_blk hsic_blk; > struct dpu_pp_blk memcolor_blk; > struct dpu_pp_blk pcc_blk; > - struct dpu_pp_blk igc_blk; > > const u32 *format_list; > u32 num_formats; > @@ -433,22 +427,18 @@ struct dpu_sspp_sub_blks { > * @maxwidth: Max pixel width supported by this mixer > * @maxblendstages: Max number of blend-stages supported > * @blendstage_base: Blend-stage register base offset > - * @gc: gamma correction block > */ > struct dpu_lm_sub_blks { > u32 maxwidth; > u32 maxblendstages; > u32 blendstage_base[MAX_BLOCKS]; > - struct dpu_pp_blk gc; > }; > > /** > * struct dpu_dspp_sub_blks: Information of DSPP block > - * @gc : gamma correction block > * @pcc: pixel color correction block > */ > struct dpu_dspp_sub_blks { > - struct dpu_pp_blk gc; > struct dpu_pp_blk pcc; > }; > > -- > 2.40.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 5d994bce696f..791a6fc8bdbf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -91,7 +91,7 @@ #define MERGE_3D_SM8150_MASK (0) -#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) +#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) @@ -449,8 +449,6 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x10007}, - .gc = { .id = DPU_DSPP_GC, .base = 0x17c0, - .len = 0x90, .version = 0x10007}, }; static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 71584cd56fd7..1230739e37d4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -127,13 +127,9 @@ enum { /** * DSPP sub-blocks * @DPU_DSPP_PCC Panel color correction block - * @DPU_DSPP_GC Gamma correction block - * @DPU_DSPP_IGC Inverse gamma correction block */ enum { DPU_DSPP_PCC = 0x1, - DPU_DSPP_GC, - DPU_DSPP_IGC, DPU_DSPP_MAX }; @@ -398,7 +394,6 @@ struct dpu_caps { * @hsic: * @memcolor: * @pcc_blk: - * @igc_blk: * @format_list: Pointer to list of supported formats * @num_formats: Number of supported formats * @virt_format_list: Pointer to list of supported formats for virtual planes @@ -419,7 +414,6 @@ struct dpu_sspp_sub_blks { struct dpu_pp_blk hsic_blk; struct dpu_pp_blk memcolor_blk; struct dpu_pp_blk pcc_blk; - struct dpu_pp_blk igc_blk; const u32 *format_list; u32 num_formats; @@ -433,22 +427,18 @@ struct dpu_sspp_sub_blks { * @maxwidth: Max pixel width supported by this mixer * @maxblendstages: Max number of blend-stages supported * @blendstage_base: Blend-stage register base offset - * @gc: gamma correction block */ struct dpu_lm_sub_blks { u32 maxwidth; u32 maxblendstages; u32 blendstage_base[MAX_BLOCKS]; - struct dpu_pp_blk gc; }; /** * struct dpu_dspp_sub_blks: Information of DSPP block - * @gc : gamma correction block * @pcc: pixel color correction block */ struct dpu_dspp_sub_blks { - struct dpu_pp_blk gc; struct dpu_pp_blk pcc; };