| Message ID | 1425d092ef4c1242646ede2bbcbc3ac945c2b274.1684425792.git.falcon@tinylab.org (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | tools/nolibc: riscv: Fix up compile error for rv32 | expand |
Hi Zhangjin, On Fri, May 19, 2023 at 01:02:12AM +0800, Zhangjin Wu wrote: > Signed-off-by: Zhangjin Wu <falcon@tinylab.org> > --- > tools/include/nolibc/arch-riscv.h | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) I'm having a comment regarding this one (which for now I've queued so that Thomas can rebase his series), please provide a real commit message that explains the purpose of the change and the solutions chosen. Feel free to copy-paste from your cover letter if that fits, it's just that I do want to see some justification for a change in the commit message itself (i.e think about the poor person seeing a bisect stop on that one). You can send me a paragraph or two and I'll happily copy them into my local copy of the rebased commit. Thank you! Willy
Hi, Willy This is a full commit message for this patch: When compile for rv32, we got such error: --- nolibc/sysroot/riscv/include/arch.h:190: Error: unrecognized opcode `ld a4,0(a3)' nolibc/sysroot/riscv/include/arch.h:194: Error: unrecognized opcode `sd a3,%lo(_auxv)(a4)' nolibc/sysroot/riscv/include/arch.h:196: Error: unrecognized opcode `sd a2,%lo(environ)(a3)' Refer to arch/riscv/include/asm/asm.h and add REG_L/REG_S macros here to let rv32 use its own lw/sw instructions. --- I will send a new version with the above full message for you, wait for a while, very sorry ;-) Best Regards, Zhangjin Wu > Hi Zhangjin, > > On Fri, May 19, 2023 at 01:02:12AM +0800, Zhangjin Wu wrote: > > Signed-off-by: Zhangjin Wu <falcon@tinylab.org> > > --- > > tools/include/nolibc/arch-riscv.h | 14 +++++++++----- > > 1 file changed, 9 insertions(+), 5 deletions(-) > > I'm having a comment regarding this one (which for now I've queued so that > Thomas can rebase his series), please provide a real commit message that > explains the purpose of the change and the solutions chosen. Feel free > to copy-paste from your cover letter if that fits, it's just that I do > want to see some justification for a change in the commit message itself > (i.e think about the poor person seeing a bisect stop on that one). > > You can send me a paragraph or two and I'll happily copy them into my > local copy of the rebased commit. > > Thank you! > Willy
On Sat, May 20, 2023 at 05:11:44PM +0800, Zhangjin Wu wrote: > Hi, Willy > > This is a full commit message for this patch: > > When compile for rv32, we got such error: > > --- > > nolibc/sysroot/riscv/include/arch.h:190: Error: unrecognized opcode `ld a4,0(a3)' > nolibc/sysroot/riscv/include/arch.h:194: Error: unrecognized opcode `sd a3,%lo(_auxv)(a4)' > nolibc/sysroot/riscv/include/arch.h:196: Error: unrecognized opcode `sd a2,%lo(environ)(a3)' > > Refer to arch/riscv/include/asm/asm.h and add REG_L/REG_S macros here to let > rv32 use its own lw/sw instructions. > > --- That's fine, thank you! > I will send a new version with the above full message for you, wait for a > while, very sorry ;-) Don't waste your time resending, I can perfectly take that one and put it into the series. Thanks! Willy
> On Sat, May 20, 2023 at 05:11:44PM +0800, Zhangjin Wu wrote: > > Hi, Willy > > > > This is a full commit message for this patch: > > > > When compile for rv32, we got such error: > > > > --- > > > > nolibc/sysroot/riscv/include/arch.h:190: Error: unrecognized opcode `ld a4,0(a3)' > > nolibc/sysroot/riscv/include/arch.h:194: Error: unrecognized opcode `sd a3,%lo(_auxv)(a4)' > > nolibc/sysroot/riscv/include/arch.h:196: Error: unrecognized opcode `sd a2,%lo(environ)(a3)' > > > > Refer to arch/riscv/include/asm/asm.h and add REG_L/REG_S macros here to let > > rv32 use its own lw/sw instructions. > > > > --- > > That's fine, thank you! > > > I will send a new version with the above full message for you, wait for a > > while, very sorry ;-) > > Don't waste your time resending, I can perfectly take that one and > put it into the series. > Thanks very much, just found the first `---` is in the wrong line, please remove the '---' lines manually ;-) When compile nolibc application for rv32, we got such errors: nolibc/sysroot/riscv/include/arch.h:190: Error: unrecognized opcode `ld a4,0(a3)' nolibc/sysroot/riscv/include/arch.h:194: Error: unrecognized opcode `sd a3,%lo(_auxv)(a4)' nolibc/sysroot/riscv/include/arch.h:196: Error: unrecognized opcode `sd a2,%lo(environ)(a3)' Refer to arch/riscv/include/asm/asm.h and add REG_L/REG_S macros here to let rv32 uses its own lw/sw instructions. Btw, I wrote some new comments for the 2nd __NR_lseek patch, it is: riscv uses the generic include/uapi/asm-generic/unistd.h, it has code like this: #if __BITS_PER_LONG == 64 && !defined(__SYSCALL_COMPAT) #define __NR_lseek __NR3264_lseek #else #define __NR_llseek __NR3264_lseek #endif There is no __NR_lseek for rv32, use __NR_llseek instead. This code is based on sysdeps/unix/sysv/linux/lseek.c of glibc. The preceeding 4 white spaces are not required for real commit messages. Best Regards, Zhangjin Wu > Thanks! > Willy
On Sat, May 20, 2023 at 06:05:10PM +0800, Zhangjin Wu wrote: > > On Sat, May 20, 2023 at 05:11:44PM +0800, Zhangjin Wu wrote: > > > Hi, Willy > > > > > > This is a full commit message for this patch: > > > > > > When compile for rv32, we got such error: > > > > > > --- > > > > > > nolibc/sysroot/riscv/include/arch.h:190: Error: unrecognized opcode `ld a4,0(a3)' > > > nolibc/sysroot/riscv/include/arch.h:194: Error: unrecognized opcode `sd a3,%lo(_auxv)(a4)' > > > nolibc/sysroot/riscv/include/arch.h:196: Error: unrecognized opcode `sd a2,%lo(environ)(a3)' > > > > > > Refer to arch/riscv/include/asm/asm.h and add REG_L/REG_S macros here to let > > > rv32 use its own lw/sw instructions. > > > > > > --- > > > > That's fine, thank you! > > > > > I will send a new version with the above full message for you, wait for a > > > while, very sorry ;-) > > > > Don't waste your time resending, I can perfectly take that one and > > put it into the series. > > > > Thanks very much, just found the first `---` is in the wrong line, please > remove the '---' lines manually ;-) > > When compile nolibc application for rv32, we got such errors: > > nolibc/sysroot/riscv/include/arch.h:190: Error: unrecognized opcode `ld a4,0(a3)' > nolibc/sysroot/riscv/include/arch.h:194: Error: unrecognized opcode `sd a3,%lo(_auxv)(a4)' > nolibc/sysroot/riscv/include/arch.h:196: Error: unrecognized opcode `sd a2,%lo(environ)(a3)' > > Refer to arch/riscv/include/asm/asm.h and add REG_L/REG_S macros here to let > rv32 uses its own lw/sw instructions. > > Btw, I wrote some new comments for the 2nd __NR_lseek patch, it is: > > riscv uses the generic include/uapi/asm-generic/unistd.h, it has code > like this: > > #if __BITS_PER_LONG == 64 && !defined(__SYSCALL_COMPAT) > #define __NR_lseek __NR3264_lseek > #else > #define __NR_llseek __NR3264_lseek > #endif > > There is no __NR_lseek for rv32, use __NR_llseek instead. > > This code is based on sysdeps/unix/sysv/linux/lseek.c of glibc. Many thanks, it's indeed better this way. > The preceeding 4 white spaces are not required for real commit messages. Sure ;-) Thanks willy
diff --git a/tools/include/nolibc/arch-riscv.h b/tools/include/nolibc/arch-riscv.h index e197fcb10ac0..7d7c4beabb8d 100644 --- a/tools/include/nolibc/arch-riscv.h +++ b/tools/include/nolibc/arch-riscv.h @@ -33,9 +33,13 @@ struct sys_stat_struct { #if __riscv_xlen == 64 #define PTRLOG "3" #define SZREG "8" +#define REG_L "ld" +#define REG_S "sd" #elif __riscv_xlen == 32 #define PTRLOG "2" #define SZREG "4" +#define REG_L "lw" +#define REG_S "sw" #endif /* Syscalls for RISCV : @@ -181,7 +185,7 @@ void __attribute__((weak,noreturn,optimize("omit-frame-pointer"))) _start(void) ".option norelax\n" "lla gp, __global_pointer$\n" ".option pop\n" - "lw a0, 0(sp)\n" // argc (a0) was in the stack + REG_L" a0, 0(sp)\n" // argc (a0) was in the stack "add a1, sp, "SZREG"\n" // argv (a1) = sp "slli a2, a0, "PTRLOG"\n" // envp (a2) = SZREG*argc ... "add a2, a2, "SZREG"\n" // + SZREG (skip null) @@ -189,14 +193,14 @@ void __attribute__((weak,noreturn,optimize("omit-frame-pointer"))) _start(void) "add a3, a2, zero\n" // iterate a3 over envp to find auxv (after NULL) "0:\n" // do { - "ld a4, 0(a3)\n" // a4 = *a3; + REG_L" a4, 0(a3)\n" // a4 = *a3; "add a3, a3, "SZREG"\n" // a3 += sizeof(void*); "bne a4, zero, 0b\n" // } while (a4); "lui a4, %hi(_auxv)\n" // a4 = &_auxv (high bits) - "sd a3, %lo(_auxv)(a4)\n" // store a3 into _auxv + REG_S" a3, %lo(_auxv)(a4)\n" // store a3 into _auxv - "lui a3, %hi(environ)\n" // a3 = &environ (high bits) - "sd a2,%lo(environ)(a3)\n" // store envp(a2) into environ + "lui a3, %hi(environ)\n" // a3 = &environ (high bits) + REG_S" a2,%lo(environ)(a3)\n"// store envp(a2) into environ "andi sp,a1,-16\n" // sp must be 16-byte aligned "call main\n" // main() returns the status code, we'll exit with it. "li a7, 93\n" // NR_exit == 93
Signed-off-by: Zhangjin Wu <falcon@tinylab.org> --- tools/include/nolibc/arch-riscv.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)