[net-next,v4,1/2] net: dsa: microchip: ksz8: Make flow control, speed, and duplex on CPU port configurable

Commit Message

Oleksij Rempel May 19, 2023, 12:46 p.m. UTC

Allow flow control, speed, and duplex settings on the CPU port to be
configurable. Previously, the speed and duplex relied on default switch
values, which limited flexibility. Additionally, flow control was
hardcoded and only functional in duplex mode. This update enhances the
configurability of these parameters.

Signed-off-by: Oleksij Rempel <[e-mail]>
Reviewed-by: Simon Horman <[e-mail]>
---
 drivers/net/dsa/microchip/ksz8.h       |  4 ++
 drivers/net/dsa/microchip/ksz8795.c    | 53 +++++++++++++++++++++++++-
 drivers/net/dsa/microchip/ksz_common.c |  1 +
 3 files changed, 56 insertions(+), 2 deletions(-)

Comments

Vladimir Oltean May 19, 2023, 2:30 p.m. UTC | #1

On Fri, May 19, 2023 at 02:46:59PM +0200, Oleksij Rempel wrote:
> +void ksz8_phylink_mac_link_up(struct ksz_device *dev, int port,
> +			      unsigned int mode, phy_interface_t interface,
> +			      struct phy_device *phydev, int speed, int duplex,
> +			      bool tx_pause, bool rx_pause)
> +{
> +	/* If the port is the CPU port, apply special handling. Only the CPU
> +	 * port is configured via global registers.
> +	 */
> +	if (dev->cpu_port == port)
> +		ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);
> +}

I'm sorry, but this is also baking in assumptions related to the
topology of the tree (that the xMII port is used as a CPU port).
The ksz8 driver may make this assumption in other places too,
but I don't want to make it even worse to fix. Is the
!dev->info->internal_phy[port] condition not enough here?

Oleksij Rempel May 19, 2023, 6:50 p.m. UTC | #2

Hi Vladimir,

On Fri, May 19, 2023 at 05:30:04PM +0300, Vladimir Oltean wrote:
> On Fri, May 19, 2023 at 02:46:59PM +0200, Oleksij Rempel wrote:
> > +void ksz8_phylink_mac_link_up(struct ksz_device *dev, int port,
> > +			      unsigned int mode, phy_interface_t interface,
> > +			      struct phy_device *phydev, int speed, int duplex,
> > +			      bool tx_pause, bool rx_pause)
> > +{
> > +	/* If the port is the CPU port, apply special handling. Only the CPU
> > +	 * port is configured via global registers.
> > +	 */
> > +	if (dev->cpu_port == port)
> > +		ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);
> > +}
> 
> I'm sorry, but this is also baking in assumptions related to the
> topology of the tree (that the xMII port is used as a CPU port).
> The ksz8 driver may make this assumption in other places too,
> but I don't want to make it even worse to fix. Is the
> !dev->info->internal_phy[port] condition not enough here?

Thank you for your feedback. I see your point. 

We need to remember that the KSZ switch series has different types of
ports. Specifically, for the KSZ8 series, there's a unique port. This
port is unique because it's the only one that can be configured with
global registers, and it is only one supports tail tagging. This special
port is already referenced in the driver by "dev->cpu_port", so I continued
using it in my patch.

It is important to note that while this port has an xMII interface, it
is not the only port that could have an xMII interface. Therefore, using
"dev->info->internal_phy" may not be the best way to identify this port,
because there can be ports that are not global/cpu, have an xMII
interface, but don't have an internal PHY.

Regards,
Oleksij

Vladimir Oltean May 19, 2023, 8:34 p.m. UTC | #3

On Fri, May 19, 2023 at 08:50:15PM +0200, Oleksij Rempel wrote:
> Thank you for your feedback. I see your point. 
> 
> We need to remember that the KSZ switch series has different types of
> ports. Specifically, for the KSZ8 series, there's a unique port. This
> port is unique because it's the only one that can be configured with
> global registers, and it is only one supports tail tagging. This special
> port is already referenced in the driver by "dev->cpu_port", so I continued
> using it in my patch.

Ok, I understand, so for the KSZ8 family, the assumption about which
port will use tail tagging is baked into the hardware.

> It is important to note that while this port has an xMII interface, it
> is not the only port that could have an xMII interface. Therefore, using
> "dev->info->internal_phy" may not be the best way to identify this port,
> because there can be ports that are not global/cpu, have an xMII
> interface, but don't have an internal PHY.

Right, but since we're talking about phylink, the goal is to identify
the xMII ports, not the CPU ports... This is a particularly denatured
case because the xMII port is global and is also the CPU port.

Vladimir Oltean May 19, 2023, 11:28 p.m. UTC | #4

On Fri, May 19, 2023 at 02:46:59PM +0200, Oleksij Rempel wrote:
> diff --git a/drivers/net/dsa/microchip/ksz8795.c b/drivers/net/dsa/microchip/ksz8795.c
> index f56fca1b1a22..9eedccbf5b7c 100644
> --- a/drivers/net/dsa/microchip/ksz8795.c
> +++ b/drivers/net/dsa/microchip/ksz8795.c
> @@ -1371,6 +1371,57 @@ void ksz8_config_cpu_port(struct dsa_switch *ds)
> +/**
> + * ksz8_cpu_port_link_up - Configures the CPU port of the switch.
> + * @dev: The KSZ device instance.
> + * @speed: The desired link speed.
> + * @duplex: The desired duplex mode.
> + * @tx_pause: If true, enables transmit pause.
> + * @rx_pause: If true, enables receive pause.
> + *
> + * Description:
> + * The function configures flow control and speed settings for the CPU
> + * port of the switch based on the desired settings, current duplex mode, and
> + * speed.
> + */
> +static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex,
> +				  bool tx_pause, bool rx_pause)
> +{
> +	u8 ctrl = 0;
> +
> +	/* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable
> +	 * at least on KSZ8873. They can have different values depending on your
> +	 * board setup.
> +	 */
> +	if (duplex) {
> +		if (tx_pause || rx_pause)
> +			ctrl |= SW_FLOW_CTRL;
> +	} else {
> +		ctrl |= SW_HALF_DUPLEX;
> +	}
> +
> +	/* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10
> +	 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0.
> +	 */
> +	if (speed == SPEED_10)
> +		ctrl |= SW_10_MBIT;
> +
> +	ksz_rmw8(dev, REG_SW_CTRL_4, SW_HALF_DUPLEX | SW_FLOW_CTRL |
> +		 SW_10_MBIT, ctrl);

REG_SW_CTRL_4 ... S_REPLACE_VID_CTRL ... dev->info->regs[P_XMII_CTRL_1] ...
at some point we will need one more consolidation effort here, since we
have at least 3 ways of reaching the same register.

> +}
> +
> +void ksz8_phylink_mac_link_up(struct ksz_device *dev, int port,
> +			      unsigned int mode, phy_interface_t interface,
> +			      struct phy_device *phydev, int speed, int duplex,
> +			      bool tx_pause, bool rx_pause)
> +{
> +	/* If the port is the CPU port, apply special handling. Only the CPU
> +	 * port is configured via global registers.
> +	 */
> +	if (dev->cpu_port == port)
> +		ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);
> +}
> +
>  static int ksz8_handle_global_errata(struct dsa_switch *ds)
>  {
>  	struct ksz_device *dev = ds->priv;
> @@ -1419,8 +1470,6 @@ int ksz8_setup(struct dsa_switch *ds)
>  	 */
>  	ds->vlan_filtering_is_global = true;
>  
> -	ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
> -
>  	/* Enable automatic fast aging when link changed detected. */
>  	ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
>  
> diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
> index a4428be5f483..6e19ad70c671 100644
> --- a/drivers/net/dsa/microchip/ksz_common.c
> +++ b/drivers/net/dsa/microchip/ksz_common.c
> @@ -210,6 +210,7 @@ static const struct ksz_dev_ops ksz8_dev_ops = {
>  	.mirror_add = ksz8_port_mirror_add,
>  	.mirror_del = ksz8_port_mirror_del,
>  	.get_caps = ksz8_get_caps,
> +	.phylink_mac_link_up = ksz8_phylink_mac_link_up,

Another future consolidation to consider: since all ksz_dev_ops now
provide .phylink_mac_link_up(), the "if" condition here is no longer
necessary:

static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
				    unsigned int mode,
				    phy_interface_t interface,
				    struct phy_device *phydev, int speed,
				    int duplex, bool tx_pause, bool rx_pause)
{
	struct ksz_device *dev = ds->priv;

	if (dev->dev_ops->phylink_mac_link_up)
		dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
						  phydev, speed, duplex,
						  tx_pause, rx_pause);
}

which reminds me of the fact that I also had a patch to remove
dev->dev_ops->phylink_mac_config():
https://patchwork.kernel.org/project/netdevbpf/patch/[e-mail]/

I give up with that patch set now, since there's zero reviewer interest.
If you want and you think it's useful, you might want to adapt it for
KSZ8873.

>  	.config_cpu_port = ksz8_config_cpu_port,
>  	.enable_stp_addr = ksz8_enable_stp_addr,
>  	.reset = ksz8_reset_switch,
> -- 
> 2.39.2
> 

Reviewed-by: Vladimir Oltean <[e-mail]>

Oleksij Rempel May 20, 2023, 4:56 a.m. UTC | #5

On Sat, May 20, 2023 at 02:28:02AM +0300, Vladimir Oltean wrote:
> > +	/* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10
> > +	 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0.
> > +	 */
> > +	if (speed == SPEED_10)
> > +		ctrl |= SW_10_MBIT;
> > +
> > +	ksz_rmw8(dev, REG_SW_CTRL_4, SW_HALF_DUPLEX | SW_FLOW_CTRL |
> > +		 SW_10_MBIT, ctrl);
> 
> REG_SW_CTRL_4 ... S_REPLACE_VID_CTRL ... dev->info->regs[P_XMII_CTRL_1] ...
> at some point we will need one more consolidation effort here, since we
> have at least 3 ways of reaching the same register.

Agree, the register access is a bit messy now. Your idea about the
regfield API sounds good. We should try it.

Should i convert this patch to use dev->info->regs?

> >  	.mirror_del = ksz8_port_mirror_del,
> >  	.get_caps = ksz8_get_caps,
> > +	.phylink_mac_link_up = ksz8_phylink_mac_link_up,
> 
> Another future consolidation to consider: since all ksz_dev_ops now
> provide .phylink_mac_link_up(), the "if" condition here is no longer
> necessary:
> 
> static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
> 				    unsigned int mode,
> 				    phy_interface_t interface,
> 				    struct phy_device *phydev, int speed,
> 				    int duplex, bool tx_pause, bool rx_pause)
> {
> 	struct ksz_device *dev = ds->priv;
> 
> 	if (dev->dev_ops->phylink_mac_link_up)
> 		dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
> 						  phydev, speed, duplex,
> 						  tx_pause, rx_pause);
> }
> 
> which reminds me of the fact that I also had a patch to remove
> dev->dev_ops->phylink_mac_config():
> https://patchwork.kernel.org/project/netdevbpf/patch/[e-mail]/
> 
> I give up with that patch set now, since there's zero reviewer interest.
> If you want and you think it's useful, you might want to adapt it for
> KSZ8873.

Sounds good. I'll take it in to my mainlining queue for KSZ8873.

> >  	.config_cpu_port = ksz8_config_cpu_port,
> >  	.enable_stp_addr = ksz8_enable_stp_addr,
> >  	.reset = ksz8_reset_switch,
> > -- 
> > 2.39.2
> > 
> 
> Reviewed-by: Vladimir Oltean <[e-mail]>
> 

Regards,
Oleksij

Oleksij Rempel May 20, 2023, 5:03 a.m. UTC | #6

On Fri, May 19, 2023 at 11:34:49PM +0300, Vladimir Oltean wrote:
> On Fri, May 19, 2023 at 08:50:15PM +0200, Oleksij Rempel wrote:
> > Thank you for your feedback. I see your point. 
> > 
> > We need to remember that the KSZ switch series has different types of
> > ports. Specifically, for the KSZ8 series, there's a unique port. This
> > port is unique because it's the only one that can be configured with
> > global registers, and it is only one supports tail tagging. This special
> > port is already referenced in the driver by "dev->cpu_port", so I continued
> > using it in my patch.
> 
> Ok, I understand, so for the KSZ8 family, the assumption about which
> port will use tail tagging is baked into the hardware.
> 
> > It is important to note that while this port has an xMII interface, it
> > is not the only port that could have an xMII interface. Therefore, using
> > "dev->info->internal_phy" may not be the best way to identify this port,
> > because there can be ports that are not global/cpu, have an xMII
> > interface, but don't have an internal PHY.
> 
> Right, but since we're talking about phylink, the goal is to identify
> the xMII ports, not the CPU ports... This is a particularly denatured
> case because the xMII port is global and is also the CPU port.

I see. Do you have any suggestions for a better or more suitable
implementation? I'm open to ideas.

Regards,
Oleksij

Vladimir Oltean May 20, 2023, 3:17 p.m. UTC | #7

On Sat, May 20, 2023 at 07:03:17AM +0200, Oleksij Rempel wrote:
> On Fri, May 19, 2023 at 11:34:49PM +0300, Vladimir Oltean wrote:
> > On Fri, May 19, 2023 at 08:50:15PM +0200, Oleksij Rempel wrote:
> > > Thank you for your feedback. I see your point. 
> > > 
> > > We need to remember that the KSZ switch series has different types of
> > > ports. Specifically, for the KSZ8 series, there's a unique port. This
> > > port is unique because it's the only one that can be configured with
> > > global registers, and it is only one supports tail tagging. This special
> > > port is already referenced in the driver by "dev->cpu_port", so I continued
> > > using it in my patch.
> > 
> > Ok, I understand, so for the KSZ8 family, the assumption about which
> > port will use tail tagging is baked into the hardware.
> > 
> > > It is important to note that while this port has an xMII interface, it
> > > is not the only port that could have an xMII interface. Therefore, using
> > > "dev->info->internal_phy" may not be the best way to identify this port,
> > > because there can be ports that are not global/cpu, have an xMII
> > > interface, but don't have an internal PHY.
> > 
> > Right, but since we're talking about phylink, the goal is to identify
> > the xMII ports, not the CPU ports... This is a particularly denatured
> > case because the xMII port is global and is also the CPU port.
> 
> I see. Do you have any suggestions for a better or more suitable
> implementation? I'm open to ideas.

Trying to answer here for both questions. In the RFC/RFT patch set I had
posted, I introduced the concept of "wacky" registers, which are registers
which should be per port (and are accessed as per-port by the driver),
but because there is a single such port in the switch, the hardware
design degenerated into moving them in the global area. Nonetheless,
treating the xMII global registers as per-port makes it possible for the
common driver to share more code between KSZ8 and others.

If you look at ksz9477_phylink_mac_link_up() - renamed to just
ksz_phylink_mac_link_up() in my patch set - hard enough, you can see
that it makes an attempt to generalize the "link up" procedure for all
switch families, via these regs and fields. At the end of that regfield
series, I theoretically converted KSZ8765/KSZ8794/KSZ8795 to reuse
ksz9477_phylink_mac_link_up(). Theoretically because no one commented
on whether the result still worked.

I think that regfields and that KSZ_WACKY_REG_FIELD_8() are an avenue
worth exploring here.

Oleksij Rempel May 21, 2023, 4:38 a.m. UTC | #8

On Sat, May 20, 2023 at 06:17:08PM +0300, Vladimir Oltean wrote:
> On Sat, May 20, 2023 at 07:03:17AM +0200, Oleksij Rempel wrote:
> > On Fri, May 19, 2023 at 11:34:49PM +0300, Vladimir Oltean wrote:
> > > On Fri, May 19, 2023 at 08:50:15PM +0200, Oleksij Rempel wrote:
> > > > Thank you for your feedback. I see your point. 
> > > > 
> > > > We need to remember that the KSZ switch series has different types of
> > > > ports. Specifically, for the KSZ8 series, there's a unique port. This
> > > > port is unique because it's the only one that can be configured with
> > > > global registers, and it is only one supports tail tagging. This special
> > > > port is already referenced in the driver by "dev->cpu_port", so I continued
> > > > using it in my patch.
> > > 
> > > Ok, I understand, so for the KSZ8 family, the assumption about which
> > > port will use tail tagging is baked into the hardware.
> > > 
> > > > It is important to note that while this port has an xMII interface, it
> > > > is not the only port that could have an xMII interface. Therefore, using
> > > > "dev->info->internal_phy" may not be the best way to identify this port,
> > > > because there can be ports that are not global/cpu, have an xMII
> > > > interface, but don't have an internal PHY.
> > > 
> > > Right, but since we're talking about phylink, the goal is to identify
> > > the xMII ports, not the CPU ports... This is a particularly denatured
> > > case because the xMII port is global and is also the CPU port.
> > 
> > I see. Do you have any suggestions for a better or more suitable
> > implementation? I'm open to ideas.
> 
> Trying to answer here for both questions. In the RFC/RFT patch set I had
> posted, I introduced the concept of "wacky" registers, which are registers
> which should be per port (and are accessed as per-port by the driver),
> but because there is a single such port in the switch, the hardware
> design degenerated into moving them in the global area. Nonetheless,
> treating the xMII global registers as per-port makes it possible for the
> common driver to share more code between KSZ8 and others.
> 
> If you look at ksz9477_phylink_mac_link_up() - renamed to just
> ksz_phylink_mac_link_up() in my patch set - hard enough, you can see
> that it makes an attempt to generalize the "link up" procedure for all
> switch families, via these regs and fields. At the end of that regfield
> series, I theoretically converted KSZ8765/KSZ8794/KSZ8795 to reuse
> ksz9477_phylink_mac_link_up(). Theoretically because no one commented
> on whether the result still worked.
> 
> I think that regfields and that KSZ_WACKY_REG_FIELD_8() are an avenue
> worth exploring here.
> 

Looks good, I like the idea with "wacky" registers!

Would you prefer that I start working on adapting your patch set to the
KSZ8873? Or should I make a review to move forward the existing patch set?

Just a heads up, I don't have access to the KSZ87xx series switches, so
I won't be able to test the changes on these models.

Let me know what you think and how we should proceed.

Regards,
Oleksij

Vladimir Oltean May 21, 2023, 10:28 a.m. UTC | #9

On Sun, May 21, 2023 at 06:38:41AM +0200, Oleksij Rempel wrote:
> Looks good, I like the idea with "wacky" registers!
> 
> Would you prefer that I start working on adapting your patch set to the
> KSZ8873? Or should I make a review to move forward the existing patch set?
> 
> Just a heads up, I don't have access to the KSZ87xx series switches, so
> I won't be able to test the changes on these models.
> 
> Let me know what you think and how we should proceed.

If we convert to regfields, the entire driver will need to be converted
(all switch families). I'd say make a best effort full conversion, and
if something breaks on the families which you could not test, surely
someone will jump to correct it. Since your KSZ8873 also has wacky registers
(btw, feel free to rename the concept to something more serious), I think
that not a lot can go wrong with a blind conversion as long as it's tested
on other hardware.

BTW, revisiting, I already found a bug in the conversion (patch 2/4):

+	} else if (mii_sel == bitval[P_RMII_SEL]) {
 		interface = PHY_INTERFACE_MODE_RGMII;
 	} else {
+		ret = ksz_regfields_read(dev, port, RF_RGMII_ID_IG_ENABLE, &ig);
+		if (WARN_ON(ret))
+			return PHY_INTERFACE_MODE_NA;
+
+		ret = ksz_regfields_read(dev, port, RF_RGMII_ID_IG_ENABLE, &eg);
						    ~~~~~~~~~~~~~~~~~~~~~
						    should have been RF_RGMII_ID_EG_ENABLE
+		if (WARN_ON(ret))
+			return PHY_INTERFACE_MODE_NA;
+
 		interface = PHY_INTERFACE_MODE_RGMII;
-		if (data8 & P_RGMII_ID_EG_ENABLE)
+		if (eg)
 			interface = PHY_INTERFACE_MODE_RGMII_TXID;
-		if (data8 & P_RGMII_ID_IG_ENABLE) {
+		if (ig) {
 			interface = PHY_INTERFACE_MODE_RGMII_RXID;
-			if (data8 & P_RGMII_ID_EG_ENABLE)
+			if (eg)
 				interface = PHY_INTERFACE_MODE_RGMII_ID;
 		}
 	}

Patch

diff --git a/drivers/net/dsa/microchip/ksz8.h b/drivers/net/dsa/microchip/ksz8.h
index e68465fdf6b9..ec02baca726f 100644
--- a/drivers/net/dsa/microchip/ksz8.h
+++ b/drivers/net/dsa/microchip/ksz8.h
@@ -58,5 +58,9 @@  int ksz8_switch_detect(struct ksz_device *dev);
 int ksz8_switch_init(struct ksz_device *dev);
 void ksz8_switch_exit(struct ksz_device *dev);
 int ksz8_change_mtu(struct ksz_device *dev, int port, int mtu);
+void ksz8_phylink_mac_link_up(struct ksz_device *dev, int port,
+			      unsigned int mode, phy_interface_t interface,
+			      struct phy_device *phydev, int speed, int duplex,
+			      bool tx_pause, bool rx_pause);
 
 #endif
diff --git a/drivers/net/dsa/microchip/ksz8795.c b/drivers/net/dsa/microchip/ksz8795.c
index f56fca1b1a22..9eedccbf5b7c 100644
--- a/drivers/net/dsa/microchip/ksz8795.c
+++ b/drivers/net/dsa/microchip/ksz8795.c
@@ -1371,6 +1371,57 @@  void ksz8_config_cpu_port(struct dsa_switch *ds)
 	}
 }
 
+/**
+ * ksz8_cpu_port_link_up - Configures the CPU port of the switch.
+ * @dev: The KSZ device instance.
+ * @speed: The desired link speed.
+ * @duplex: The desired duplex mode.
+ * @tx_pause: If true, enables transmit pause.
+ * @rx_pause: If true, enables receive pause.
+ *
+ * Description:
+ * The function configures flow control and speed settings for the CPU
+ * port of the switch based on the desired settings, current duplex mode, and
+ * speed.
+ */
+static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex,
+				  bool tx_pause, bool rx_pause)
+{
+	u8 ctrl = 0;
+
+	/* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable
+	 * at least on KSZ8873. They can have different values depending on your
+	 * board setup.
+	 */
+	if (duplex) {
+		if (tx_pause || rx_pause)
+			ctrl |= SW_FLOW_CTRL;
+	} else {
+		ctrl |= SW_HALF_DUPLEX;
+	}
+
+	/* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10
+	 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0.
+	 */
+	if (speed == SPEED_10)
+		ctrl |= SW_10_MBIT;
+
+	ksz_rmw8(dev, REG_SW_CTRL_4, SW_HALF_DUPLEX | SW_FLOW_CTRL |
+		 SW_10_MBIT, ctrl);
+}
+
+void ksz8_phylink_mac_link_up(struct ksz_device *dev, int port,
+			      unsigned int mode, phy_interface_t interface,
+			      struct phy_device *phydev, int speed, int duplex,
+			      bool tx_pause, bool rx_pause)
+{
+	/* If the port is the CPU port, apply special handling. Only the CPU
+	 * port is configured via global registers.
+	 */
+	if (dev->cpu_port == port)
+		ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);
+}
+
 static int ksz8_handle_global_errata(struct dsa_switch *ds)
 {
 	struct ksz_device *dev = ds->priv;
@@ -1419,8 +1470,6 @@  int ksz8_setup(struct dsa_switch *ds)
 	 */
 	ds->vlan_filtering_is_global = true;
 
-	ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
-
 	/* Enable automatic fast aging when link changed detected. */
 	ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
 
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index a4428be5f483..6e19ad70c671 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -210,6 +210,7 @@  static const struct ksz_dev_ops ksz8_dev_ops = {
 	.mirror_add = ksz8_port_mirror_add,
 	.mirror_del = ksz8_port_mirror_del,
 	.get_caps = ksz8_get_caps,
+	.phylink_mac_link_up = ksz8_phylink_mac_link_up,
 	.config_cpu_port = ksz8_config_cpu_port,
 	.enable_stp_addr = ksz8_enable_stp_addr,
 	.reset = ksz8_reset_switch,