| Message ID | 897779a0-1a1f-4193-9dd3-bc4f87e73e3c@kili.mountain (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | drm/msm/dpu: signedness bug in dpu_encoder_phys_cmd_tearcheck_config() | expand |
On 2023-05-22 10:48:01, Dan Carpenter wrote: > The "vsync_hz" variable is used to store negative error codes so it > needs to be signed for the error checking to work correctly. Nicely spotted, but it it looks like we have more to fix then. The type returned by dpu_kms_get_clk_rate() is u64: - Perhaps the int used in this patch is too small (though 19.2MHz vsync clock ought to fit); - That function should also return a signed number as part of this contract. - Marijn > > Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") > Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > index 74470d068622..b29e6d1ba7f6 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > @@ -320,7 +320,7 @@ static void dpu_encoder_phys_cmd_tearcheck_config( > struct dpu_hw_tear_check tc_cfg = { 0 }; > struct drm_display_mode *mode; > bool tc_enable = true; > - u32 vsync_hz; > + int vsync_hz; > struct dpu_kms *dpu_kms; > > if (!phys_enc->hw_pp) { > -- > 2.39.2 >
On Mon, 22 May 2023 at 11:47, Marijn Suijten <marijn.suijten@somainline.org> wrote: > > On 2023-05-22 10:48:01, Dan Carpenter wrote: > > The "vsync_hz" variable is used to store negative error codes so it > > needs to be signed for the error checking to work correctly. > > Nicely spotted, but it it looks like we have more to fix then. The type > returned by dpu_kms_get_clk_rate() is u64: > > - Perhaps the int used in this patch is too small (though 19.2MHz vsync > clock ought to fit); > - That function should also return a signed number as part of this > contract. Please also include freedreno@ to the cc list when sending v2. > > - Marijn > > > > > Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") > > Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > index 74470d068622..b29e6d1ba7f6 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > @@ -320,7 +320,7 @@ static void dpu_encoder_phys_cmd_tearcheck_config( > > struct dpu_hw_tear_check tc_cfg = { 0 }; > > struct drm_display_mode *mode; > > bool tc_enable = true; > > - u32 vsync_hz; > > + int vsync_hz; > > struct dpu_kms *dpu_kms; > > > > if (!phys_enc->hw_pp) { > > -- > > 2.39.2 > >
On Mon, May 22, 2023 at 10:47:50AM +0200, Marijn Suijten wrote: > On 2023-05-22 10:48:01, Dan Carpenter wrote: > > The "vsync_hz" variable is used to store negative error codes so it > > needs to be signed for the error checking to work correctly. > > Nicely spotted, but it it looks like we have more to fix then. The type > returned by dpu_kms_get_clk_rate() is u64: > That's a good point. Although the type of clk_get_rate() is unsigned long so probably unsigned long is enough. > - Perhaps the int used in this patch is too small (though 19.2MHz vsync > clock ought to fit); > - That function should also return a signed number as part of this > contract. What about if we just return 0 instead of -EINVAL? That would match what clk_get_rate() does. Also let me change the type to unsigned long. regards, dan carpenter
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 74470d068622..b29e6d1ba7f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -320,7 +320,7 @@ static void dpu_encoder_phys_cmd_tearcheck_config( struct dpu_hw_tear_check tc_cfg = { 0 }; struct drm_display_mode *mode; bool tc_enable = true; - u32 vsync_hz; + int vsync_hz; struct dpu_kms *dpu_kms; if (!phys_enc->hw_pp) {
The "vsync_hz" variable is used to store negative error codes so it needs to be signed for the error checking to work correctly. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)