| Message ID | 20230526150044.31553-2-alejandro.vallejo@cloud.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Automatic IBRS support | expand |
On 26/05/2023 4:00 pm, Alejandro Vallejo wrote: > This is AMD's version of Intel's Enhanced IBRS. Exposed in CPUID > and toggled in EFER. AIBRS and EIBRS are very much not the same, and I argued hard to not have Linux confuse the too, but alas. Don't mention EIBRS at all. Simply "Auto IBRS is a new feature in AMD Zen4 CPUs and late, intended to reduce the overhead involved with operating IBRS", or something along these lines. > diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c > index 5d0c64a45f..e487885a5c 100644 > --- a/tools/misc/xen-cpuid.c > +++ b/tools/misc/xen-cpuid.c > @@ -200,6 +200,8 @@ static const char *const str_e21a[32] = > [ 2] = "lfence+", > [ 6] = "nscb", > > + [ 8] = "auto-ibrs", > + This wants to be: [ 6] = "nscb", + [ 8] = "auto-ibrs", as they are adjacent with names in two columns. Gaps are only for discontinuities in numbering. > diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h > index 777041425e..e3952f62bc 100644 > --- a/xen/include/public/arch-x86/cpufeatureset.h > +++ b/xen/include/public/arch-x86/cpufeatureset.h > @@ -287,6 +287,7 @@ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */ > /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ > XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */ > XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base (and limit too) */ > +XEN_CPUFEATURE(AUTOMATIC_IBRS, 11*32+ 8) /* HW can handle IBRS on its own */ Were possible, we want to use the same names. AUTO_IBRS is fine here, and shorter to use throughout Xen. Furthermore, it must match the cpu_has_* name, and that's already in the better form. ~Andrew
On Fri, May 26, 2023 at 05:46:51PM +0100, Andrew Cooper wrote: > AIBRS and EIBRS are very much not the same, and I argued hard to not > have Linux confuse the too, but alas. > > Don't mention EIBRS at all. > > Simply "Auto IBRS is a new feature in AMD Zen4 CPUs and late, intended > to reduce the overhead involved with operating IBRS", or something along > these lines. Sure. I did go out of my way to avoid ambiguityin the code, but it's true the commit message is unfortunate. > > > diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c > > index 5d0c64a45f..e487885a5c 100644 > > --- a/tools/misc/xen-cpuid.c > > +++ b/tools/misc/xen-cpuid.c > > @@ -200,6 +200,8 @@ static const char *const str_e21a[32] = > > [ 2] = "lfence+", > > [ 6] = "nscb", > > > > + [ 8] = "auto-ibrs", > > + > > This wants to be: > > [ 6] = "nscb", > + [ 8] = "auto-ibrs", > > as they are adjacent with names in two columns. Gaps are only for > discontinuities in numbering. > > [...] > > Were possible, we want to use the same names. AUTO_IBRS is fine here, > and shorter to use throughout Xen. Sure to both. Alejandro
diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c index cca0f19d93..f5ce9f9795 100644 --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -317,6 +317,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str) {"lfence+", 0x80000021, NA, CPUID_REG_EAX, 2, 1}, {"nscb", 0x80000021, NA, CPUID_REG_EAX, 6, 1}, + {"auto-ibrs", 0x80000021, NA, CPUID_REG_EAX, 8, 1}, {"cpuid-user-dis", 0x80000021, NA, CPUID_REG_EAX, 17, 1}, {"maxhvleaf", 0x40000000, NA, CPUID_REG_EAX, 0, 8}, diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 5d0c64a45f..e487885a5c 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -200,6 +200,8 @@ static const char *const str_e21a[32] = [ 2] = "lfence+", [ 6] = "nscb", + [ 8] = "auto-ibrs", + /* 16 */ [17] = "cpuid-user-dis", }; diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 50235f098d..d5947a6826 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -161,6 +161,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_amd_ssbd boot_cpu_has(X86_FEATURE_AMD_SSBD) #define cpu_has_virt_ssbd boot_cpu_has(X86_FEATURE_VIRT_SSBD) #define cpu_has_ssb_no boot_cpu_has(X86_FEATURE_SSB_NO) +#define cpu_has_auto_ibrs boot_cpu_has(X86_FEATURE_AUTOMATIC_IBRS) /* CPUID level 0x00000007:0.edx */ #define cpu_has_avx512_4vnniw boot_cpu_has(X86_FEATURE_AVX512_4VNNIW) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 082fb2e0d9..73d0af2615 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -175,6 +175,7 @@ #define EFER_NXE (_AC(1, ULL) << 11) /* No Execute Enable */ #define EFER_SVME (_AC(1, ULL) << 12) /* Secure Virtual Machine Enable */ #define EFER_FFXSE (_AC(1, ULL) << 14) /* Fast FXSAVE/FXRSTOR */ +#define EFER_AIBRSE (_AC(1, ULL) << 21) /* Automatic IBRS Enable */ #define EFER_KNOWN_MASK \ (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 777041425e..e3952f62bc 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -287,6 +287,7 @@ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */ /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */ XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base (and limit too) */ +XEN_CPUFEATURE(AUTOMATIC_IBRS, 11*32+ 8) /* HW can handle IBRS on its own */ XEN_CPUFEATURE(CPUID_USER_DIS, 11*32+17) /* CPUID disable for CPL > 0 software */ /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
This is AMD's version of Intel's Enhanced IBRS. Exposed in CPUID and toggled in EFER. Signed-off-by: Alejandro Vallejo <alejandro.vallejo@cloud.com> --- tools/libs/light/libxl_cpuid.c | 1 + tools/misc/xen-cpuid.c | 2 ++ xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/msr-index.h | 1 + xen/include/public/arch-x86/cpufeatureset.h | 1 + 5 files changed, 6 insertions(+)