diff mbox series

[v2] arm64: dts: imx8-ss-dma: assign default clock rate for lpuarts

Message ID 20230526153854.469239-1-shenwei.wang@nxp.com (mailing list archive)
State New, archived
Headers show
Series [v2] arm64: dts: imx8-ss-dma: assign default clock rate for lpuarts | expand

Commit Message

Shenwei Wang May 26, 2023, 3:38 p.m. UTC 
Add the assigned-clocks and assigned-clock-rates properties for the
LPUARTx nodes. Without these properties, the default clock rate
used would be 0, which can cause the UART ports to fail when open.

Fixes: 35f4e9d7530f ("arm64: dts: imx8: split adma ss into dma and audio ss")
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
---
 V2:
  - refactor the comments and add the fix tag per Fabio's feedback

 arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

--
2.34.1

Comments

Fabio Estevam May 26, 2023, 3:41 p.m. UTC | #1 
On Fri, May 26, 2023 at 12:39 PM Shenwei Wang <shenwei.wang@nxp.com> wrote:
>
> Add the assigned-clocks and assigned-clock-rates properties for the
> LPUARTx nodes. Without these properties, the default clock rate
> used would be 0, which can cause the UART ports to fail when open.
>
> Fixes: 35f4e9d7530f ("arm64: dts: imx8: split adma ss into dma and audio ss")
> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Shawn Guo May 27, 2023, 1 p.m. UTC | #2 
On Fri, May 26, 2023 at 10:38:54AM -0500, Shenwei Wang wrote:
> Add the assigned-clocks and assigned-clock-rates properties for the
> LPUARTx nodes. Without these properties, the default clock rate
> used would be 0, which can cause the UART ports to fail when open.
> 
> Fixes: 35f4e9d7530f ("arm64: dts: imx8: split adma ss into dma and audio ss")
> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index 2dce8f2ee3ea..adb98a72bdfd 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -90,6 +90,8 @@  lpuart0: serial@5a060000 {
 		clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
 			 <&uart0_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <80000000>;
 		power-domains = <&pd IMX_SC_R_UART_0>;
 		status = "disabled";
 	};
@@ -100,6 +102,8 @@  lpuart1: serial@5a070000 {
 		clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
 			 <&uart1_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <80000000>;
 		power-domains = <&pd IMX_SC_R_UART_1>;
 		status = "disabled";
 	};
@@ -110,6 +114,8 @@  lpuart2: serial@5a080000 {
 		clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
 			 <&uart2_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <80000000>;
 		power-domains = <&pd IMX_SC_R_UART_2>;
 		status = "disabled";
 	};
@@ -120,6 +126,8 @@  lpuart3: serial@5a090000 {
 		clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
 			 <&uart3_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <80000000>;
 		power-domains = <&pd IMX_SC_R_UART_3>;
 		status = "disabled";
 	};