| Message ID | 20230524150152.136371-1-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Reset only one lane in case of MFD | expand |
From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Thursday, May 25, 2023 7:19 PM
To: Kahola, Mika <mika.kahola@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for drm/i915/mtl: Reset only one lane in case of MFD
Patch Details
Series:
drm/i915/mtl: Reset only one lane in case of MFD
URL:
https://patchwork.freedesktop.org/series/118308/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/index.html
CI Bug Log - changes from CI_DRM_13187_full -> Patchwork_118308v1_full
Summary
FAILURE
Serious unknown changes coming with Patchwork_118308v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_118308v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
No changes in participating hosts
Possible new issues
Here are the unknown changes that may have been introduced in Patchwork_118308v1_full:
IGT changes
Possible regressions
* igt@kms_invalid_mode@bad-htotal:
* shard-snb: NOTRUN -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-snb1/igt@kms_invalid_mode@bad-htotal.html>
This is incorrect. The code path of the patch doesn’t touch Sandybridge at all.
New tests
New tests have been introduced between CI_DRM_13187_full and Patchwork_118308v1_full:
New IGT tests (280)
* igt@kms_flip@2x-dpms-vs-vblank-race@ab-hdmi-a1-hdmi-a2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race@ac-hdmi-a1-hdmi-a2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race@bc-hdmi-a1-hdmi-a2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1:
* Statuses : 3 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
* Statuses : 3 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-c-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-b-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-c-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-2:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-c-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-a-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-2:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-d-hdmi-a-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-a-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-hdmi-a-2:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-a-hdmi-a-1:
* Statuses : 3 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-b-hdmi-a-1:
* Statuses : 3 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-c-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1:
* Statuses : 3 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-a-vga-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-b-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-b-vga-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-c-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-a-hdmi-a-1:
* Statuses : 3 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-a-vga-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-b-hdmi-a-1:
* Statuses : 3 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-b-vga-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-c-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-a-hdmi-a-1:
* Statuses : 1 pass(s) 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-b-hdmi-a-1:
* Statuses : 1 pass(s) 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-b-hdmi-a-2:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-d-hdmi-a-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-c-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-20x20@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-20x20@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-20x20@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-1:
* Statuses : 2 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1:
* Statuses : 3 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-b-hdmi-a-1:
* Statuses : 3 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-d-hdmi-a-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1:
* Statuses : 3 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1:
* Statuses : 3 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-d-hdmi-a-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-1:
* Statuses : 3 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-1:
* Statuses : 3 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-2:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c-hdmi-a-1:
* Statuses : 1 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling:
* Statuses :
* Exec time: [None] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-vga-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-2:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-vga-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-vga-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b-vga-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-hdmi-a-1:
* Statuses : 2 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-c-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-c-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b-hdmi-a-1:
* Statuses : 2 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-c-hdmi-a-1:
* Statuses : 1 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-1:
* Statuses : 2 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-hdmi-a-1:
* Statuses : 3 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-hdmi-a-1:
* Statuses : 1 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-c-hdmi-a-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-a-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-a-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-a-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b-dp-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b-hdmi-a-1:
* Statuses : 2 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b-hdmi-a-2:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b-vga-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-c-dp-1:
* Statuses : 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-c-hdmi-a-1:
* Statuses : 1 pass(s) 1 skip(s)
* Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-d-hdmi-a-1:
* Statuses : 1 pass(s)
* Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_118308v1_full that come from known issues:
IGT changes
Issues hit
* igt@gem_exec_fair@basic-throttle@rcs0:
* shard-glk: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html> (i915#2842<https://gitlab.freedesktop.org/drm/intel/issues/2842>)
* igt@gem_lmem_swapping@basic:
* shard-glk: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-glk6/igt@gem_lmem_swapping@basic.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#4613<https://gitlab.freedesktop.org/drm/intel/issues/4613>)
* igt@gem_spin_batch@spin-each:
* shard-apl: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-apl6/igt@gem_spin_batch@spin-each.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-apl3/igt@gem_spin_batch@spin-each.html> (i915#2898<https://gitlab.freedesktop.org/drm/intel/issues/2898>)
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
* shard-glk: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-glk6/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#3886<https://gitlab.freedesktop.org/drm/intel/issues/3886>) +1 similar issue
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs:
* shard-glk: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-glk6/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +15 similar issues
* igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
* shard-apl: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html> -> ABORT<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-apl4/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html> (i915#180<https://gitlab.freedesktop.org/drm/intel/issues/180>)
* igt@kms_flip@flip-vs-expired-vblank@c-dp1:
* shard-apl: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-apl4/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-apl4/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html> (i915#79<https://gitlab.freedesktop.org/drm/intel/issues/79>)
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
* shard-glk: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-glk6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html> (IGT#6<https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6> / fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +10 similar issues
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1 (NEW):
* {shard-rkl}: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1.html> (i915#5176<https://gitlab.freedesktop.org/drm/intel/issues/5176>) +1 similar issue
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1 (NEW):
* {shard-rkl}: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-rkl-7/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1.html> (i915#4579<https://gitlab.freedesktop.org/drm/intel/issues/4579> / i915#5176<https://gitlab.freedesktop.org/drm/intel/issues/5176>) +1 similar issue
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-1 (NEW):
* shard-glk: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-glk6/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-1.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#4579<https://gitlab.freedesktop.org/drm/intel/issues/4579>) +2 similar issues
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b-hdmi-a-1:
* shard-snb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-snb1/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b-hdmi-a-1.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#4579<https://gitlab.freedesktop.org/drm/intel/issues/4579>) +11 similar issues
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-hdmi-a-1 (NEW):
* shard-snb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-snb1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-hdmi-a-1.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +14 similar issues
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2 (NEW):
* {shard-rkl}: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-rkl-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html> (i915#4579<https://gitlab.freedesktop.org/drm/intel/issues/4579> / i915#5235<https://gitlab.freedesktop.org/drm/intel/issues/5235>)
Possible fixes
* igt@gem_exec_fair@basic-none@bcs0:
* {shard-rkl}: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-rkl-1/igt@gem_exec_fair@basic-none@bcs0.html> (i915#2842<https://gitlab.freedesktop.org/drm/intel/issues/2842>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-rkl-7/igt@gem_exec_fair@basic-none@bcs0.html> +1 similar issue
* igt@gem_exec_fair@basic-pace-share@rcs0:
* shard-glk: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html> (i915#2842<https://gitlab.freedesktop.org/drm/intel/issues/2842>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html>
* {shard-tglu}: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html> (i915#2842<https://gitlab.freedesktop.org/drm/intel/issues/2842>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-tglu-7/igt@gem_exec_fair@basic-pace-share@rcs0.html>
* igt@gem_lmem_swapping@smem-oom@lmem0:
* {shard-dg1}: TIMEOUT<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html> (i915#5493<https://gitlab.freedesktop.org/drm/intel/issues/5493>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html>
* igt@gem_spin_batch@user-each:
* shard-apl: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-apl3/igt@gem_spin_batch@user-each.html> (i915#2898<https://gitlab.freedesktop.org/drm/intel/issues/2898>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-apl6/igt@gem_spin_batch@user-each.html>
* igt@gen9_exec_parse@allowed-single:
* shard-glk: ABORT<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-glk2/igt@gen9_exec_parse@allowed-single.html> (i915#5566<https://gitlab.freedesktop.org/drm/intel/issues/5566>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-glk6/igt@gen9_exec_parse@allowed-single.html>
* igt@i915_pm_dc@dc6-dpms:
* {shard-tglu}: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-tglu-5/igt@i915_pm_dc@dc6-dpms.html> (i915#3989<https://gitlab.freedesktop.org/drm/intel/issues/3989> / i915#454<https://gitlab.freedesktop.org/drm/intel/issues/454>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-tglu-4/igt@i915_pm_dc@dc6-dpms.html>
* igt@i915_pm_dc@dc9-dpms:
* {shard-tglu}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-tglu-7/igt@i915_pm_dc@dc9-dpms.html> (i915#4281<https://gitlab.freedesktop.org/drm/intel/issues/4281>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-tglu-10/igt@i915_pm_dc@dc9-dpms.html>
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-rkl-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html> (i915#1937<https://gitlab.freedesktop.org/drm/intel/issues/1937> / i915#4579<https://gitlab.freedesktop.org/drm/intel/issues/4579>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html>
* igt@i915_pm_rpm@modeset-lpsp-stress:
* {shard-rkl}: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress.html> (i915#1397<https://gitlab.freedesktop.org/drm/intel/issues/1397>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress.html> +1 similar issue
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
* shard-apl: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html> (IGT#6<https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6> / i915#2346<https://gitlab.freedesktop.org/drm/intel/issues/2346>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html>
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
* shard-glk: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html> (i915#79<https://gitlab.freedesktop.org/drm/intel/issues/79>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118308v1/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html> +1 similar issue
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Build changes
* Linux: CI_DRM_13187 -> Patchwork_118308v1
CI-20190529: 20190529
CI_DRM_13187: e72bc131968e21d9deeae208605481c93581f142 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7303: 8f09a9f1da506db907b549bb477f3233b5416733 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118308v1: e72bc131968e21d9deeae208605481c93581f142 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
Looks good, I only have some nitpicks. On Wed, 2023-05-24 at 18:01 +0300, Mika Kahola wrote: > In case when only two or less lanes are owned such as MFD (DP-alt with x2 lanes) > we need to reset only one lane (lane0). With only x2 lanes we don't need > to poll for the phy current status on both lanes since only the owned lane > will respond. It would be nice to explain why it is so. > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39 ++++++++++++-------- > 1 file changed, 23 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index ee6902118860..b8c812c5b33f 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2528,13 +2528,23 @@ static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask) > return val; > } > > -/* FIXME: Some Type-C cases need not reset both the lanes. Handle those cases. */ > -static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port port, > +static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, > + struct intel_encoder *encoder, > bool lane_reversal) > { > + enum port port = encoder->port; > enum phy phy = intel_port_to_phy(i915, port); > + u8 fia_max = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)); Logically, we don't care about "fia_max" in this function, we only care whether one or two lanes should be handled. In all places we use fia_max, we only check if it is > 2. So I think it would be clearer to have the > 2 here already and call the variable something else. Additionally, "> 2" looks slightly magic (without knowing the reason, as stated in my first comment). Is there any more self-explanatory symbol we could used? > u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : > INTEL_CX0_LANE0; > + u32 lane_pipe_reset = fia_max > 2 ? > + XELPDP_LANE_PIPE_RESET(0) | > + XELPDP_LANE_PIPE_RESET(1) : > + XELPDP_LANE_PIPE_RESET(0); > + u32 lane_phy_current_status = fia_max > 2 ? > + XELPDP_LANE_PHY_CURRENT_STATUS(0) | > + XELPDP_LANE_PHY_CURRENT_STATUS(1) : > + XELPDP_LANE_PHY_CURRENT_STATUS(0); It was already logically like this in the code, so not directly related to this patch, but is there any reason why we don't need to include more lanes in the reset? I mean, we're only handling lanes 0 and 1. If we have 4 lanes, the other two never need to be reset? -- Cheers, Luca.
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika > Kahola > Sent: Wednesday, May 24, 2023 8:32 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH] drm/i915/mtl: Reset only one lane in case of MFD > > In case when only two or less lanes are owned such as MFD (DP-alt with x2 > lanes) we need to reset only one lane (lane0). With only x2 lanes we don't > need to poll for the phy current status on both lanes since only the owned > lane will respond. > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Thanks and Regards, Arun R Murthy -------------------- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39 ++++++++++++-------- > 1 file changed, 23 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index ee6902118860..b8c812c5b33f 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2528,13 +2528,23 @@ static u32 intel_cx0_get_pclk_refclk_ack(u8 > lane_mask) > return val; > } > > -/* FIXME: Some Type-C cases need not reset both the lanes. Handle those > cases. */ -static void intel_cx0_phy_lane_reset(struct drm_i915_private > *i915, enum port port, > +static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, > + struct intel_encoder *encoder, > bool lane_reversal) > { > + enum port port = encoder->port; > enum phy phy = intel_port_to_phy(i915, port); > + u8 fia_max = > +intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)); > u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : > INTEL_CX0_LANE0; > + u32 lane_pipe_reset = fia_max > 2 ? > + XELPDP_LANE_PIPE_RESET(0) | > + XELPDP_LANE_PIPE_RESET(1) : > + XELPDP_LANE_PIPE_RESET(0); > + u32 lane_phy_current_status = fia_max > 2 ? > + XELPDP_LANE_PHY_CURRENT_STATUS(0) > | > + XELPDP_LANE_PHY_CURRENT_STATUS(1) : > + XELPDP_LANE_PHY_CURRENT_STATUS(0); > > if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port), > > XELPDP_PORT_BUF_SOC_PHY_READY, > @@ -2545,23 +2555,24 @@ static void intel_cx0_phy_lane_reset(struct > drm_i915_private *i915, enum port po > > intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), > XELPDP_LANE_PIPE_RESET(0) | > XELPDP_LANE_PIPE_RESET(1), > - XELPDP_LANE_PIPE_RESET(0) | > XELPDP_LANE_PIPE_RESET(1)); > + lane_pipe_reset); > > if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port), > - > XELPDP_LANE_PHY_CURRENT_STATUS(0) | > - > XELPDP_LANE_PHY_CURRENT_STATUS(1), > - > XELPDP_LANE_PHY_CURRENT_STATUS(0) | > - > XELPDP_LANE_PHY_CURRENT_STATUS(1), > + lane_phy_current_status, > lane_phy_current_status, > > XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) > drm_warn(&i915->drm, "PHY %c failed to bring out of Lane > reset after %dus.\n", > phy_name(phy), > XELPDP_PORT_RESET_START_TIMEOUT_US); > > intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port), > - > intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), > + intel_cx0_get_pclk_refclk_request(fia_max > 2 ? > + INTEL_CX0_BOTH_LANES : > + INTEL_CX0_LANE0), > intel_cx0_get_pclk_refclk_request(lane_mask)); > > if (__intel_de_wait_for_register(i915, > XELPDP_PORT_CLOCK_CTL(port), > - > intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), > + > intel_cx0_get_pclk_refclk_ack(fia_max > 2 ? > + > INTEL_CX0_BOTH_LANES : > + > INTEL_CX0_LANE0), > > intel_cx0_get_pclk_refclk_ack(lane_mask), > > XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) > drm_warn(&i915->drm, "PHY %c failed to request refclk after > %dus.\n", @@ -2571,13 +2582,9 @@ static void > intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port po > CX0_P2_STATE_RESET); > intel_cx0_setup_powerdown(i915, port); > > - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), > - XELPDP_LANE_PIPE_RESET(0) | > XELPDP_LANE_PIPE_RESET(1), > - 0); > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, > 0); > > - if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), > - XELPDP_LANE_PHY_CURRENT_STATUS(0) | > - XELPDP_LANE_PHY_CURRENT_STATUS(1), > + if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), > +lane_phy_current_status, > XELPDP_PORT_RESET_END_TIMEOUT)) > drm_warn(&i915->drm, "PHY %c failed to bring out of Lane > reset after %dms.\n", > phy_name(phy), > XELPDP_PORT_RESET_END_TIMEOUT); @@ -2705,7 +2712,7 @@ static void > intel_cx0pll_enable(struct intel_encoder *encoder, > intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal); > > /* 2. Bring PHY out of reset. */ > - intel_cx0_phy_lane_reset(i915, encoder->port, lane_reversal); > + intel_cx0_phy_lane_reset(i915, encoder, lane_reversal); > > /* > * 3. Change Phy power state to Ready. > -- > 2.34.1
> -----Original Message----- > From: Luca Coelho <luca@coelho.fi> > Sent: Tuesday, May 30, 2023 11:38 AM > To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Reset only one lane in case of MFD > > Looks good, I only have some nitpicks. > > On Wed, 2023-05-24 at 18:01 +0300, Mika Kahola wrote: > > In case when only two or less lanes are owned such as MFD (DP-alt with > > x2 lanes) we need to reset only one lane (lane0). With only x2 lanes > > we don't need to poll for the phy current status on both lanes since > > only the owned lane will respond. > > It would be nice to explain why it is so. > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39 > > ++++++++++++-------- > > 1 file changed, 23 insertions(+), 16 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > index ee6902118860..b8c812c5b33f 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > @@ -2528,13 +2528,23 @@ static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask) > > return val; > > } > > > > -/* FIXME: Some Type-C cases need not reset both the lanes. Handle > > those cases. */ -static void intel_cx0_phy_lane_reset(struct > > drm_i915_private *i915, enum port port, > > +static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, > > + struct intel_encoder *encoder, > > bool lane_reversal) > > { > > + enum port port = encoder->port; > > enum phy phy = intel_port_to_phy(i915, port); > > + u8 fia_max = > > +intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)); > > Logically, we don't care about "fia_max" in this function, we only care whether one or two lanes should be handled. In all places > we use fia_max, we only check if it is > 2. So I think it would be clearer to have the > 2 here already and call the variable > something else. > > Additionally, "> 2" looks slightly magic (without knowing the reason, as stated in my first comment). Is there any more self- > explanatory symbol we could used? I admit, it's not that clear when you look at it first time. It only means that all lanes are in use and we should in that case reset all lanes. Maybe switching to Boolean instead something like this bool all_lanes = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2; And do the reset routines based on this? > > > u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : > > INTEL_CX0_LANE0; > > + u32 lane_pipe_reset = fia_max > 2 ? > > + XELPDP_LANE_PIPE_RESET(0) | > > + XELPDP_LANE_PIPE_RESET(1) : > > + XELPDP_LANE_PIPE_RESET(0); > > + u32 lane_phy_current_status = fia_max > 2 ? > > + XELPDP_LANE_PHY_CURRENT_STATUS(0) | > > + XELPDP_LANE_PHY_CURRENT_STATUS(1) : > > + XELPDP_LANE_PHY_CURRENT_STATUS(0); > > It was already logically like this in the code, so not directly related to this patch, but is there any reason why we don't need to > include more lanes in the reset? I mean, we're only handling lanes 0 and 1. If we have 4 lanes, the other two never need to be > reset? There are lanes and then there are lanes. FIA has 4 main lanes with are muxed into 2 data lanes and here we only reset these data lanes. It's confusing as we have lanes defined for two different meanings. Thanks for the review and comments! -Mika- > > -- > Cheers, > Luca.
On Tue, 2023-05-30 at 09:30 +0000, Kahola, Mika wrote: > > -----Original Message----- > > From: Luca Coelho <luca@coelho.fi> > > Sent: Tuesday, May 30, 2023 11:38 AM > > To: Kahola, Mika <mika.kahola@intel.com>; intel- > > gfx@lists.freedesktop.org > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Reset only one lane > > in case of MFD > > > > Looks good, I only have some nitpicks. > > > > On Wed, 2023-05-24 at 18:01 +0300, Mika Kahola wrote: > > > In case when only two or less lanes are owned such as MFD (DP-alt > > > with > > > x2 lanes) we need to reset only one lane (lane0). With only x2 > > > lanes > > > we don't need to poll for the phy current status on both lanes > > > since > > > only the owned lane will respond. > > > > It would be nice to explain why it is so. > > > > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39 > > > ++++++++++++-------- > > > 1 file changed, 23 insertions(+), 16 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > > index ee6902118860..b8c812c5b33f 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > > @@ -2528,13 +2528,23 @@ static u32 > > > intel_cx0_get_pclk_refclk_ack(u8 lane_mask) > > > return val; > > > } > > > > > > -/* FIXME: Some Type-C cases need not reset both the lanes. > > > Handle > > > those cases. */ -static void intel_cx0_phy_lane_reset(struct > > > drm_i915_private *i915, enum port port, > > > +static void intel_cx0_phy_lane_reset(struct drm_i915_private > > > *i915, > > > + struct intel_encoder > > > *encoder, > > > bool lane_reversal) > > > { > > > + enum port port = encoder->port; > > > enum phy phy = intel_port_to_phy(i915, port); > > > + u8 fia_max = > > > +intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)); > > > > Logically, we don't care about "fia_max" in this function, we only > > care whether one or two lanes should be handled. In all places > > we use fia_max, we only check if it is > 2. So I think it would be > > clearer to have the > 2 here already and call the variable > > something else. > > > > Additionally, "> 2" looks slightly magic (without knowing the > > reason, as stated in my first comment). Is there any more self- > > explanatory symbol we could used? > I admit, it's not that clear when you look at it first time. It only > means that all lanes are in use and we should in that case reset all > lanes. Maybe switching to Boolean instead something like this > > bool all_lanes = > intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2; > > And do the reset routines based on this? Sounds good. > > > u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : > > > INTEL_CX0_LANE0; > > > + u32 lane_pipe_reset = fia_max > 2 ? > > > + XELPDP_LANE_PIPE_RESET(0) | > > > + XELPDP_LANE_PIPE_RESET(1) : > > > + XELPDP_LANE_PIPE_RESET(0); > > > + u32 lane_phy_current_status = fia_max > 2 ? > > > + > > > XELPDP_LANE_PHY_CURRENT_STATUS(0) | > > > + > > > XELPDP_LANE_PHY_CURRENT_STATUS(1) : > > > + > > > XELPDP_LANE_PHY_CURRENT_STATUS(0); > > > > It was already logically like this in the code, so not directly > > related to this patch, but is there any reason why we don't need to > > include more lanes in the reset? I mean, we're only handling lanes > > 0 and 1. If we have 4 lanes, the other two never need to be > > reset? > There are lanes and then there are lanes. FIA has 4 main lanes with > are muxed into 2 data lanes and here we only reset these data lanes. > It's confusing as we have lanes defined for two different meanings. Okay, that clarifies it! We should probably have been calling them fia_lanes and data_lanes to distinguish, but make these changes now. This also clarifies why we reset only one or both data lanes. A small paragraph explaining this would be nice in the commit log and/or as a comment in the function. > Thanks for the review and comments! You're welcome! You're helping me learn.
> -----Original Message----- > From: Luca Coelho <luca@coelho.fi> > Sent: Tuesday, May 30, 2023 1:08 PM > To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Reset only one lane in case of MFD > > On Tue, 2023-05-30 at 09:30 +0000, Kahola, Mika wrote: > > > -----Original Message----- > > > From: Luca Coelho <luca@coelho.fi> > > > Sent: Tuesday, May 30, 2023 11:38 AM > > > To: Kahola, Mika <mika.kahola@intel.com>; intel- > > > gfx@lists.freedesktop.org > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Reset only one lane > > > in case of MFD > > > > > > Looks good, I only have some nitpicks. > > > > > > On Wed, 2023-05-24 at 18:01 +0300, Mika Kahola wrote: > > > > In case when only two or less lanes are owned such as MFD (DP-alt > > > > with > > > > x2 lanes) we need to reset only one lane (lane0). With only x2 > > > > lanes we don't need to poll for the phy current status on both > > > > lanes since only the owned lane will respond. > > > > > > It would be nice to explain why it is so. > > > > > > > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39 > > > > ++++++++++++-------- > > > > 1 file changed, 23 insertions(+), 16 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > > > index ee6902118860..b8c812c5b33f 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > > > > @@ -2528,13 +2528,23 @@ static u32 > > > > intel_cx0_get_pclk_refclk_ack(u8 lane_mask) > > > > return val; > > > > } > > > > > > > > -/* FIXME: Some Type-C cases need not reset both the lanes. > > > > Handle > > > > those cases. */ -static void intel_cx0_phy_lane_reset(struct > > > > drm_i915_private *i915, enum port port, > > > > +static void intel_cx0_phy_lane_reset(struct drm_i915_private > > > > *i915, > > > > + struct intel_encoder > > > > *encoder, > > > > bool lane_reversal) > > > > { > > > > + enum port port = encoder->port; > > > > enum phy phy = intel_port_to_phy(i915, port); > > > > + u8 fia_max = > > > > +intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)); > > > > > > Logically, we don't care about "fia_max" in this function, we only > > > care whether one or two lanes should be handled. In all places we > > > use fia_max, we only check if it is > 2. So I think it would be > > > clearer to have the > 2 here already and call the variable something > > > else. > > > > > > Additionally, "> 2" looks slightly magic (without knowing the > > > reason, as stated in my first comment). Is there any more self- > > > explanatory symbol we could used? > > I admit, it's not that clear when you look at it first time. It only > > means that all lanes are in use and we should in that case reset all > > lanes. Maybe switching to Boolean instead something like this > > > > bool all_lanes = > > intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2; > > > > And do the reset routines based on this? > > Sounds good. > > > > > > u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : > > > > INTEL_CX0_LANE0; > > > > + u32 lane_pipe_reset = fia_max > 2 ? > > > > + XELPDP_LANE_PIPE_RESET(0) | > > > > + XELPDP_LANE_PIPE_RESET(1) : > > > > + XELPDP_LANE_PIPE_RESET(0); > > > > + u32 lane_phy_current_status = fia_max > 2 ? > > > > + > > > > XELPDP_LANE_PHY_CURRENT_STATUS(0) | > > > > + > > > > XELPDP_LANE_PHY_CURRENT_STATUS(1) : > > > > + > > > > XELPDP_LANE_PHY_CURRENT_STATUS(0); > > > > > > It was already logically like this in the code, so not directly > > > related to this patch, but is there any reason why we don't need to > > > include more lanes in the reset? I mean, we're only handling lanes > > > 0 and 1. If we have 4 lanes, the other two never need to be reset? > > There are lanes and then there are lanes. FIA has 4 main lanes with > > are muxed into 2 data lanes and here we only reset these data lanes. > > It's confusing as we have lanes defined for two different meanings. > > Okay, that clarifies it! We should probably have been calling them fia_lanes and data_lanes to distinguish, but make these > changes now. I will try to clarify these naming conventions. I spin another round of this patch which hopefully is more self-explanatory. -Mika- > > This also clarifies why we reset only one or both data lanes. A small paragraph explaining this would be nice in the commit log > and/or as a comment in the function. > > > > Thanks for the review and comments! > > You're welcome! You're helping me learn.
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index ee6902118860..b8c812c5b33f 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2528,13 +2528,23 @@ static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask) return val; } -/* FIXME: Some Type-C cases need not reset both the lanes. Handle those cases. */ -static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port port, +static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, + struct intel_encoder *encoder, bool lane_reversal) { + enum port port = encoder->port; enum phy phy = intel_port_to_phy(i915, port); + u8 fia_max = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)); u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0; + u32 lane_pipe_reset = fia_max > 2 ? + XELPDP_LANE_PIPE_RESET(0) | + XELPDP_LANE_PIPE_RESET(1) : + XELPDP_LANE_PIPE_RESET(0); + u32 lane_phy_current_status = fia_max > 2 ? + XELPDP_LANE_PHY_CURRENT_STATUS(0) | + XELPDP_LANE_PHY_CURRENT_STATUS(1) : + XELPDP_LANE_PHY_CURRENT_STATUS(0); if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port), XELPDP_PORT_BUF_SOC_PHY_READY, @@ -2545,23 +2555,24 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port po intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1), - XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1)); + lane_pipe_reset); if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port), - XELPDP_LANE_PHY_CURRENT_STATUS(0) | - XELPDP_LANE_PHY_CURRENT_STATUS(1), - XELPDP_LANE_PHY_CURRENT_STATUS(0) | - XELPDP_LANE_PHY_CURRENT_STATUS(1), + lane_phy_current_status, lane_phy_current_status, XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US); intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port), - intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), + intel_cx0_get_pclk_refclk_request(fia_max > 2 ? + INTEL_CX0_BOTH_LANES : + INTEL_CX0_LANE0), intel_cx0_get_pclk_refclk_request(lane_mask)); if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port), - intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), + intel_cx0_get_pclk_refclk_ack(fia_max > 2 ? + INTEL_CX0_BOTH_LANES : + INTEL_CX0_LANE0), intel_cx0_get_pclk_refclk_ack(lane_mask), XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n", @@ -2571,13 +2582,9 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port po CX0_P2_STATE_RESET); intel_cx0_setup_powerdown(i915, port); - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), - XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1), - 0); + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0); - if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), - XELPDP_LANE_PHY_CURRENT_STATUS(0) | - XELPDP_LANE_PHY_CURRENT_STATUS(1), + if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status, XELPDP_PORT_RESET_END_TIMEOUT)) drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n", phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT); @@ -2705,7 +2712,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal); /* 2. Bring PHY out of reset. */ - intel_cx0_phy_lane_reset(i915, encoder->port, lane_reversal); + intel_cx0_phy_lane_reset(i915, encoder, lane_reversal); /* * 3. Change Phy power state to Ready.
In case when only two or less lanes are owned such as MFD (DP-alt with x2 lanes) we need to reset only one lane (lane0). With only x2 lanes we don't need to poll for the phy current status on both lanes since only the owned lane will respond. Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 39 ++++++++++++-------- 1 file changed, 23 insertions(+), 16 deletions(-)