| Message ID | 20230526145402.450-4-walker.chen@starfivetech.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Add TDM audio on StarFive JH7110 | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes, riscv/for-next or riscv/master |
On Fri, 26 May 2023 22:54:02 +0800, Walker Chen wrote: > Add the tdm controller node and pins configuration of tdm for the > StarFive JH7110 SoC. > > Signed-off-by: Walker Chen <walker.chen@starfivetech.com> > --- > .../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++++++++ > 2 files changed, 61 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 1155b97b593d..19b5954ee72d 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -214,6 +214,40 @@ > slew-rate = <0>; > }; > }; > + > + tdm0_pins: tdm0-pins { > + tdm0-pins-tx { Use consistent naming, so tdm_pins: tdm-0 { tx-pins { > + pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD, > + GPOEN_ENABLE, > + GPI_NONE)>; > + bias-pull-up; > + drive-strength = <2>; > + input-disable; > + input-schmitt-disable; > + slew-rate = <0>; > + }; > + > + tdm0-pins-rx { rx-pins { > + pinmux = <GPIOMUX(61, GPOUT_HIGH, > + GPOEN_DISABLE, > + GPI_SYS_TDM_RXD)>; > + input-enable; > + }; > + > + tdm0-pins-sync { sync-pins { > + pinmux = <GPIOMUX(63, GPOUT_HIGH, > + GPOEN_DISABLE, > + GPI_SYS_TDM_SYNC)>; > + input-enable; > + }; > + > + tdm0-pins-pcmclk { pcmclk-pins { > + pinmux = <GPIOMUX(38, GPOUT_HIGH, > + GPOEN_DISABLE, > + GPI_SYS_TDM_CLK)>; > + input-enable; > + }; > + }; > }; > > &uart0 { > @@ -221,3 +255,9 @@ > pinctrl-0 = <&uart0_pins>; > status = "okay"; > }; > + > +&tdm { > + pinctrl-names = "default"; > + pinctrl-0 = <&tdm0_pins>; pinctrl-0 = <&tdm_pins>; Best regards, Hal > + status = "okay"; > +};
On 2023/5/31 14:23, Hal Feng wrote: > On Fri, 26 May 2023 22:54:02 +0800, Walker Chen wrote: >> Add the tdm controller node and pins configuration of tdm for the >> StarFive JH7110 SoC. >> >> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> >> --- >> .../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++ >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++++++++ >> 2 files changed, 61 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> index 1155b97b593d..19b5954ee72d 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> @@ -214,6 +214,40 @@ >> slew-rate = <0>; >> }; >> }; >> + >> + tdm0_pins: tdm0-pins { >> + tdm0-pins-tx { > > Use consistent naming, so > > tdm_pins: tdm-0 { > tx-pins { > >> + pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD, >> + GPOEN_ENABLE, >> + GPI_NONE)>; >> + bias-pull-up; >> + drive-strength = <2>; >> + input-disable; >> + input-schmitt-disable; >> + slew-rate = <0>; >> + }; >> + >> + tdm0-pins-rx { > > rx-pins { > >> + pinmux = <GPIOMUX(61, GPOUT_HIGH, >> + GPOEN_DISABLE, >> + GPI_SYS_TDM_RXD)>; >> + input-enable; >> + }; >> + >> + tdm0-pins-sync { > > sync-pins { > >> + pinmux = <GPIOMUX(63, GPOUT_HIGH, >> + GPOEN_DISABLE, >> + GPI_SYS_TDM_SYNC)>; >> + input-enable; >> + }; >> + >> + tdm0-pins-pcmclk { > > pcmclk-pins { > >> + pinmux = <GPIOMUX(38, GPOUT_HIGH, >> + GPOEN_DISABLE, >> + GPI_SYS_TDM_CLK)>; >> + input-enable; >> + }; >> + }; >> }; >> >> &uart0 { >> @@ -221,3 +255,9 @@ >> pinctrl-0 = <&uart0_pins>; >> status = "okay"; >> }; >> + >> +&tdm { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&tdm0_pins>; > > pinctrl-0 = <&tdm_pins>; > > Best regards, > Hal OK, I'll update these node's name in the next submit. Thanks. Best regards, Walker
On Wed, 31 May 2023 14:30:19 +0800, Walker Chen wrote: > On 2023/5/31 14:23, Hal Feng wrote: >> On Fri, 26 May 2023 22:54:02 +0800, Walker Chen wrote: >>> Add the tdm controller node and pins configuration of tdm for the >>> StarFive JH7110 SoC. >>> >>> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> >>> --- >>> .../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++ >>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++++++++ >>> 2 files changed, 61 insertions(+) >>> >>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >>> index 1155b97b593d..19b5954ee72d 100644 >>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >>> @@ -214,6 +214,40 @@ >>> slew-rate = <0>; >>> }; >>> }; >>> + >>> + tdm0_pins: tdm0-pins { >>> + tdm0-pins-tx { >> >> Use consistent naming, so >> >> tdm_pins: tdm-0 { >> tx-pins { >> >>> + pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD, >>> + GPOEN_ENABLE, >>> + GPI_NONE)>; >>> + bias-pull-up; >>> + drive-strength = <2>; >>> + input-disable; >>> + input-schmitt-disable; >>> + slew-rate = <0>; >>> + }; >>> + >>> + tdm0-pins-rx { >> >> rx-pins { >> >>> + pinmux = <GPIOMUX(61, GPOUT_HIGH, >>> + GPOEN_DISABLE, >>> + GPI_SYS_TDM_RXD)>; >>> + input-enable; >>> + }; >>> + >>> + tdm0-pins-sync { >> >> sync-pins { >> >>> + pinmux = <GPIOMUX(63, GPOUT_HIGH, >>> + GPOEN_DISABLE, >>> + GPI_SYS_TDM_SYNC)>; >>> + input-enable; >>> + }; >>> + >>> + tdm0-pins-pcmclk { >> >> pcmclk-pins { >> >>> + pinmux = <GPIOMUX(38, GPOUT_HIGH, >>> + GPOEN_DISABLE, >>> + GPI_SYS_TDM_CLK)>; >>> + input-enable; >>> + }; >>> + }; >>> }; >>> >>> &uart0 { >>> @@ -221,3 +255,9 @@ >>> pinctrl-0 = <&uart0_pins>; >>> status = "okay"; >>> }; >>> + >>> +&tdm { >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&tdm0_pins>; >> >> pinctrl-0 = <&tdm_pins>; >> >> Best regards, >> Hal > > OK, I'll update these node's name in the next submit. > Thanks. With that fixed, Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Best regards, Hal
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 1155b97b593d..19b5954ee72d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -214,6 +214,40 @@ slew-rate = <0>; }; }; + + tdm0_pins: tdm0-pins { + tdm0-pins-tx { + pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD, + GPOEN_ENABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + tdm0-pins-rx { + pinmux = <GPIOMUX(61, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_RXD)>; + input-enable; + }; + + tdm0-pins-sync { + pinmux = <GPIOMUX(63, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_SYNC)>; + input-enable; + }; + + tdm0-pins-pcmclk { + pinmux = <GPIOMUX(38, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_CLK)>; + input-enable; + }; + }; }; &uart0 { @@ -221,3 +255,9 @@ pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&tdm { + pinctrl-names = "default"; + pinctrl-0 = <&tdm0_pins>; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 866313570a7e..cfda6fb0d91b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -366,6 +366,27 @@ status = "disabled"; }; + tdm: tdm@10090000 { + compatible = "starfive,jh7110-tdm"; + reg = <0x0 0x10090000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>, + <&syscrg JH7110_SYSCLK_TDM_APB>, + <&syscrg JH7110_SYSCLK_TDM_INTERNAL>, + <&syscrg JH7110_SYSCLK_TDM_TDM>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&tdm_ext>; + clock-names = "tdm_ahb", "tdm_apb", + "tdm_internal", "tdm", + "mclk_inner", "tdm_ext"; + resets = <&syscrg JH7110_SYSRST_TDM_AHB>, + <&syscrg JH7110_SYSRST_TDM_APB>, + <&syscrg JH7110_SYSRST_TDM_CORE>; + dmas = <&dma 20>, <&dma 21>; + dma-names = "rx","tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + stgcrg: clock-controller@10230000 { compatible = "starfive,jh7110-stgcrg"; reg = <0x0 0x10230000 0x0 0x10000>;
Add the tdm controller node and pins configuration of tdm for the StarFive JH7110 SoC. Signed-off-by: Walker Chen <walker.chen@starfivetech.com> --- .../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++++++++ 2 files changed, 61 insertions(+)