| Message ID | 20230601121331.487207-6-fbarrat@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Various xive fixes | expand |
On 6/1/23 14:13, Frederic Barrat wrote: > The Thread Interrupt Management Area (TIMA) can be accessed through 4 > ports, targeted by the address. The base address of a TIMA > is using port 0 and the other ports are 0x80 apart. Using one port or > another can be useful to balance the load on the snoop buses. With > skiboot and linux, we currently use port 0, but as it tends to be > busy, another hypervisor is using port 1 for TIMA access. > > The port address bits fall in between the special op indication > bits (the 2 MSBs) and the register offset bits (the 6 LSBs). They are > "don't care" for the hardware when processing a TIMA operation. This > patch filters out those port address bits so that a TIMA operation can > be triggered using any port. > > It is also true for indirect access (through the IC BAR) and it's > actually nothing new, it was already the case on P9. Which helps here, > as the TIMA handling code is common between P9 (xive) and P10 (xive2). > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > hw/intc/pnv_xive2.c | 4 ++++ > hw/intc/xive.c | 2 +- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index 5fc4240216..ec1edeb385 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -1666,6 +1666,8 @@ static void pnv_xive2_tm_write(void *opaque, hwaddr offset, > bool gen1_tima_os = > xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; > > + offset &= TM_ADDRESS_MASK; > + > /* TODO: should we switch the TM ops table instead ? */ > if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) { > xive2_tm_push_os_ctx(xptr, tctx, offset, value, size); > @@ -1685,6 +1687,8 @@ static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) > bool gen1_tima_os = > xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; > > + offset &= TM_ADDRESS_MASK; > + > /* TODO: should we switch the TM ops table instead ? */ > if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) { > return xive2_tm_pull_os_ctx(xptr, tctx, offset, size); > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index ebe399bc09..5204c14b87 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -500,7 +500,7 @@ static const XiveTmOp xive_tm_operations[] = { > static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) > { > uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; > - uint32_t op_offset = offset & 0xFFF; > + uint32_t op_offset = offset & TM_ADDRESS_MASK; > int i; > > for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) {
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 5fc4240216..ec1edeb385 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1666,6 +1666,8 @@ static void pnv_xive2_tm_write(void *opaque, hwaddr offset, bool gen1_tima_os = xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; + offset &= TM_ADDRESS_MASK; + /* TODO: should we switch the TM ops table instead ? */ if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) { xive2_tm_push_os_ctx(xptr, tctx, offset, value, size); @@ -1685,6 +1687,8 @@ static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) bool gen1_tima_os = xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; + offset &= TM_ADDRESS_MASK; + /* TODO: should we switch the TM ops table instead ? */ if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) { return xive2_tm_pull_os_ctx(xptr, tctx, offset, size); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index ebe399bc09..5204c14b87 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -500,7 +500,7 @@ static const XiveTmOp xive_tm_operations[] = { static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) { uint8_t page_offset = (offset >> TM_SHIFT) & 0x3; - uint32_t op_offset = offset & 0xFFF; + uint32_t op_offset = offset & TM_ADDRESS_MASK; int i; for (i = 0; i < ARRAY_SIZE(xive_tm_operations); i++) {
The Thread Interrupt Management Area (TIMA) can be accessed through 4 ports, targeted by the address. The base address of a TIMA is using port 0 and the other ports are 0x80 apart. Using one port or another can be useful to balance the load on the snoop buses. With skiboot and linux, we currently use port 0, but as it tends to be busy, another hypervisor is using port 1 for TIMA access. The port address bits fall in between the special op indication bits (the 2 MSBs) and the register offset bits (the 6 LSBs). They are "don't care" for the hardware when processing a TIMA operation. This patch filters out those port address bits so that a TIMA operation can be triggered using any port. It is also true for indirect access (through the IC BAR) and it's actually nothing new, it was already the case on P9. Which helps here, as the TIMA handling code is common between P9 (xive) and P10 (xive2). Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> --- hw/intc/pnv_xive2.c | 4 ++++ hw/intc/xive.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-)