| Message ID | 20230602191501.4138433-1-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm: bridge: tc358767: increase PLL lock time delay | expand |
On 6/2/23 21:15, Lucas Stach wrote: > From: David Jander <david@protonic.nl> > > The PLL often fails to lock with this delay. The new value was > determined by trial and error increasing the delay bit by bit > until the error did not occurr anymore even after several tries. > Then double that value was taken as the minimum delay to be safe. > > Signed-off-by: David Jander <david@protonic.nl> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/gpu/drm/bridge/tc358767.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c > index 91f7cb56a654..46916ae30f8f 100644 > --- a/drivers/gpu/drm/bridge/tc358767.c > +++ b/drivers/gpu/drm/bridge/tc358767.c > @@ -501,7 +501,7 @@ static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) > return ret; > > /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ > - usleep_range(3000, 6000); > + usleep_range(15000, 20000); The comment above does not seem to match either value, please fix. With that fixed: Reviewed-by: Marek Vasut <marex@denx.de>
On 6/2/23 21:15, Lucas Stach wrote: > From: David Jander <david@protonic.nl> > > The PLL often fails to lock with this delay. The new value was > determined by trial and error increasing the delay bit by bit > until the error did not occurr anymore even after several tries. > Then double that value was taken as the minimum delay to be safe. > > Signed-off-by: David Jander <david@protonic.nl> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Marek Vasut <marex@denx.de> # TC9595 Reviewed-by: Marek Vasut <marex@denx.de>
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 91f7cb56a654..46916ae30f8f 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -501,7 +501,7 @@ static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) return ret; /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ - usleep_range(3000, 6000); + usleep_range(15000, 20000); return 0; }