| Message ID | 20230510062234.201499-12-yoshihiro.shimoda.uh@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | PCI: rcar-gen4: Add R-Car Gen4 PCIe support | expand |
On Wed, May 10, 2023 at 03:22:23PM +0900, Yoshihiro Shimoda wrote: > Add dw_pcie_link_set_max_cap_width() to set PCI_EXP_LNKCAP_MLW. > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0] > field there is another one which needs to be updated. It's > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at > the very least the maximum link-width capability CSR won't expose > the actual maximum capability. > > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, > Version 4.60a, March 2015, p.1032 > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, > Version 4.70a, March 2016, p.1065 > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, > Version 4.90a, March 2016, p.1057 > ... > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint, > Version 5.40a, March 2019, p.1396 > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, > Version 5.40a, March 2019, p.1266 > > The commit description is suggested by Serge Semin. > > Suggested-by: Serge Semin <fancer.lancer@gmail.com> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > --- > drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 5dc423dd2f21..8b2978c6eb23 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -758,6 +758,21 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); > } > > +static void dw_pcie_link_set_max_cap_width(struct dw_pcie *pci, int num_lanes) > +{ > + u32 val; > + u8 cap; > + > + if (!num_lanes) > + return; > + > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + val = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); > + val &= ~PCI_EXP_LNKCAP_MLW; > + val |= num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT; > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, val); Once again. Please move this code to the dw_pcie_link_set_max_link_width() method as I already asked here: https://lore.kernel.org/linux-pci/20230501195753.o3qfcs7qyergccnr@mobilestation/ There is no point in creating a separate method for the action which is implied by the already defined and incomplete dw_pcie_link_set_max_link_width() function. Also as we already agreed please replace the hard-coded bitwise shift operation with the FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes) statement. -Serge(y) > +} > + > void dw_pcie_iatu_detect(struct dw_pcie *pci) > { > int max_region, ob, ib; > @@ -1040,4 +1055,5 @@ void dw_pcie_setup(struct dw_pcie *pci) > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); > > dw_pcie_link_set_max_link_width(pci, pci->num_lanes); > + dw_pcie_link_set_max_cap_width(pci, pci->num_lanes); > } > -- > 2.25.1 >
Hello Serge, > From: Serge Semin, Sent: Monday, June 5, 2023 7:59 PM > > On Wed, May 10, 2023 at 03:22:23PM +0900, Yoshihiro Shimoda wrote: > > Add dw_pcie_link_set_max_cap_width() to set PCI_EXP_LNKCAP_MLW. > > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with > > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0] > > field there is another one which needs to be updated. It's > > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at > > the very least the maximum link-width capability CSR won't expose > > the actual maximum capability. > > > > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, > > Version 4.60a, March 2015, p.1032 > > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, > > Version 4.70a, March 2016, p.1065 > > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, > > Version 4.90a, March 2016, p.1057 > > ... > > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint, > > Version 5.40a, March 2019, p.1396 > > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, > > Version 5.40a, March 2019, p.1266 > > > > The commit description is suggested by Serge Semin. > > > > Suggested-by: Serge Semin <fancer.lancer@gmail.com> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > --- > > drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index 5dc423dd2f21..8b2978c6eb23 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -758,6 +758,21 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) > > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); > > } > > > > +static void dw_pcie_link_set_max_cap_width(struct dw_pcie *pci, int num_lanes) > > +{ > > > + u32 val; > > + u8 cap; > > + > > + if (!num_lanes) > > + return; > > + > > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > > + val = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); > > + val &= ~PCI_EXP_LNKCAP_MLW; > > + val |= num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT; > > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, val); > > Once again. Please move this code to the > dw_pcie_link_set_max_link_width() method as I already asked here: <snip URL> I'm sorry for misunderstanding your previous comment... > There is no point in creating a separate method for the action which > is implied by the already defined and incomplete > dw_pcie_link_set_max_link_width() function. > > Also as we already agreed please replace the hard-coded bitwise shift > operation with the FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes) > statement. I got it. Best regards, Yoshihiro Shimoda > -Serge(y) > > > +} > > + > > void dw_pcie_iatu_detect(struct dw_pcie *pci) > > { > > int max_region, ob, ib; > > @@ -1040,4 +1055,5 @@ void dw_pcie_setup(struct dw_pcie *pci) > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); > > > > dw_pcie_link_set_max_link_width(pci, pci->num_lanes); > > + dw_pcie_link_set_max_cap_width(pci, pci->num_lanes); > > } > > -- > > 2.25.1 > >
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 5dc423dd2f21..8b2978c6eb23 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -758,6 +758,21 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); } +static void dw_pcie_link_set_max_cap_width(struct dw_pcie *pci, int num_lanes) +{ + u32 val; + u8 cap; + + if (!num_lanes) + return; + + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + val = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_MLW; + val |= num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT; + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, val); +} + void dw_pcie_iatu_detect(struct dw_pcie *pci) { int max_region, ob, ib; @@ -1040,4 +1055,5 @@ void dw_pcie_setup(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); dw_pcie_link_set_max_link_width(pci, pci->num_lanes); + dw_pcie_link_set_max_cap_width(pci, pci->num_lanes); }
Add dw_pcie_link_set_max_cap_width() to set PCI_EXP_LNKCAP_MLW. In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0] field there is another one which needs to be updated. It's LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at the very least the maximum link-width capability CSR won't expose the actual maximum capability. [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 4.60a, March 2015, p.1032 [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 4.70a, March 2016, p.1065 [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 4.90a, March 2016, p.1057 ... [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint, Version 5.40a, March 2019, p.1396 [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 5.40a, March 2019, p.1266 The commit description is suggested by Serge Semin. Suggested-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)