| Message ID | 20230605110724.21391-1-andy.chiu@sifive.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | riscv: Add vector ISA support | expand |
Hi Andy, On Mon, Jun 05, 2023 at 11:07:20AM +0000, Andy Chiu wrote: > Some extensions use .option arch directive to selectively enable certain > extensions in parts of its assembly code. For example, Zbb uses it to > inform assmebler to emit bit manipulation instructions. However, > supporting of this directive only exist on GNU assembler and has not > landed on clang at the moment, making TOOLCHAIN_HAS_ZBB depend on > AS_IS_GNU. > > While it is still under review at https://reviews.llvm.org/D123515, the > upcoming Vector patch also requires this feature in assembler. Thus, > provide Kconfig AS_HAS_OPTION_ARCH to detect such feature. Then > TOOLCHAIN_HAS_XXX will be turned on automatically when the feature land. Just an FYI, this change has landed in LLVM main, so it should be in LLVM 17 in a few months: https://github.com/llvm/llvm-project/commit/9e8ed3403c191ab9c4903e8eeb8f732ff8a43cb4 If you have to spin another revision for some reason, consider updating the Phabricator link to that one, as I expect that link to remain more stable in the long run over the Phabricator one, as LLVM is planning to eventually move away from Phabricator to GitHub pull requests. I don't think this is worth respinning on its own (obviously, heh). The rest of the change still looks good to me, thanks again for taking this up. > Suggested-by: Nathan Chancellor <nathan@kernel.org> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Nathan Chancellor <nathan@kernel.org> > Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > --- > arch/riscv/Kconfig | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 348c0fa1fc8c..1019b519d590 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -262,6 +262,12 @@ config RISCV_DMA_NONCOHERENT > config AS_HAS_INSN > def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) > > +config AS_HAS_OPTION_ARCH > + # https://reviews.llvm.org/D123515 > + def_bool y > + depends on $(as-instr, .option arch$(comma) +m) > + depends on !$(as-instr, .option arch$(comma) -i) > + > source "arch/riscv/Kconfig.socs" > source "arch/riscv/Kconfig.errata" > > @@ -466,7 +472,7 @@ config TOOLCHAIN_HAS_ZBB > depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbb) > depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb) > depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900 > - depends on AS_IS_GNU > + depends on AS_HAS_OPTION_ARCH > > config RISCV_ISA_ZBB > bool "Zbb extension support for bit manipulation instructions" > -- > 2.17.1 >
On Mon, Jun 05, 2023 at 08:48:32AM -0700, Nathan Chancellor wrote: > Just an FYI, this change has landed in LLVM main, so it should be in > LLVM 17 in a few months: Great! :)
On Mon, 05 Jun 2023 11:06:57 +0000, Andy Chiu wrote: > This is the v21 patch series for adding Vector extension support in > Linux. Please refer to [1] for the introduction of the patchset. The > v21 patch series was aimed to solve build issues from v19, provide usage > guideline for the prctl interface, and address review comments on v20. > > Thank every one who has been reviewing, suggesting on the topic. Hope > this get a step closer to the final merge. > > [...] Applied, thanks! [01/27] riscv: Rename __switch_to_aux() -> fpu https://git.kernel.org/palmer/c/419d5d38ac5d [02/27] riscv: Extending cpufeature.c to detect V-extension https://git.kernel.org/palmer/c/dc6667a4e7e3 [03/27] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 https://git.kernel.org/palmer/c/162e4df137c1 [04/27] riscv: Add new csr defines related to vector extension https://git.kernel.org/palmer/c/b5665d2a9432 [05/27] riscv: Clear vector regfile on bootup https://git.kernel.org/palmer/c/6b533828726a [06/27] riscv: Disable Vector Instructions for kernel itself https://git.kernel.org/palmer/c/74abe5a39d3a [07/27] riscv: Introduce Vector enable/disable helpers https://git.kernel.org/palmer/c/0a3381a01dcc [08/27] riscv: Introduce riscv_v_vsize to record size of Vector context https://git.kernel.org/palmer/c/7017858eb2d7 [09/27] riscv: Introduce struct/helpers to save/restore per-task Vector state https://git.kernel.org/palmer/c/03c3fcd9941a [10/27] riscv: Add task switch support for vector https://git.kernel.org/palmer/c/3a2df6323def [11/27] riscv: Allocate user's vector context in the first-use trap https://git.kernel.org/palmer/c/cd054837243b [12/27] riscv: Add ptrace vector support https://git.kernel.org/palmer/c/0c59922c769a [13/27] riscv: signal: check fp-reserved words unconditionally https://git.kernel.org/palmer/c/a45cedaa1ac0 [14/27] riscv: signal: Add sigcontext save/restore for vector https://git.kernel.org/palmer/c/8ee0b41898fa [15/27] riscv: signal: Report signal frame size to userspace via auxv https://git.kernel.org/palmer/c/e92f469b0771 [16/27] riscv: signal: validate altstack to reflect Vector https://git.kernel.org/palmer/c/76e22fdc2c26 [17/27] riscv: prevent stack corruption by reserving task_pt_regs(p) early https://git.kernel.org/palmer/c/c7cdd96eca28 [18/27] riscv: kvm: Add V extension to KVM ISA https://git.kernel.org/palmer/c/bf78f1ea6e51 [19/27] riscv: KVM: Add vector lazy save/restore support https://git.kernel.org/palmer/c/0f4b82579716 [20/27] riscv: hwcap: change ELF_HWCAP to a function https://git.kernel.org/palmer/c/50724efcb370 [21/27] riscv: Add prctl controls for userspace vector management https://git.kernel.org/palmer/c/1fd96a3e9d5d [22/27] riscv: Add sysctl to set the default vector rule for new processes https://git.kernel.org/palmer/c/7ca7a7b9b635 [23/27] riscv: detect assembler support for .option arch https://git.kernel.org/palmer/c/e4bb020f3dbb [24/27] riscv: Enable Vector code to be built https://git.kernel.org/palmer/c/fa8e7cce55da [25/27] riscv: Add documentation for Vector https://git.kernel.org/palmer/c/04a4722eeede [26/27] selftests: Test RISC-V Vector prctl interface https://git.kernel.org/palmer/c/7cf6198ce22d [27/27] selftests: add .gitignore file for RISC-V hwprobe https://git.kernel.org/palmer/c/1e72695137ef Best regards,
Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Mon, 5 Jun 2023 11:06:57 +0000 you wrote: > This is the v21 patch series for adding Vector extension support in > Linux. Please refer to [1] for the introduction of the patchset. The > v21 patch series was aimed to solve build issues from v19, provide usage > guideline for the prctl interface, and address review comments on v20. > > Thank every one who has been reviewing, suggesting on the topic. Hope > this get a step closer to the final merge. > > [...] Here is the summary with links: - [-next,v21,01/27] riscv: Rename __switch_to_aux() -> fpu https://git.kernel.org/riscv/c/419d5d38ac5d - [-next,v21,02/27] riscv: Extending cpufeature.c to detect V-extension https://git.kernel.org/riscv/c/dc6667a4e7e3 - [-next,v21,03/27] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 https://git.kernel.org/riscv/c/162e4df137c1 - [-next,v21,04/27] riscv: Add new csr defines related to vector extension https://git.kernel.org/riscv/c/b5665d2a9432 - [-next,v21,05/27] riscv: Clear vector regfile on bootup https://git.kernel.org/riscv/c/6b533828726a - [-next,v21,06/27] riscv: Disable Vector Instructions for kernel itself https://git.kernel.org/riscv/c/74abe5a39d3a - [-next,v21,07/27] riscv: Introduce Vector enable/disable helpers https://git.kernel.org/riscv/c/0a3381a01dcc - [-next,v21,08/27] riscv: Introduce riscv_v_vsize to record size of Vector context https://git.kernel.org/riscv/c/7017858eb2d7 - [-next,v21,09/27] riscv: Introduce struct/helpers to save/restore per-task Vector state https://git.kernel.org/riscv/c/03c3fcd9941a - [-next,v21,10/27] riscv: Add task switch support for vector https://git.kernel.org/riscv/c/3a2df6323def - [-next,v21,11/27] riscv: Allocate user's vector context in the first-use trap https://git.kernel.org/riscv/c/cd054837243b - [-next,v21,12/27] riscv: Add ptrace vector support https://git.kernel.org/riscv/c/0c59922c769a - [-next,v21,13/27] riscv: signal: check fp-reserved words unconditionally https://git.kernel.org/riscv/c/a45cedaa1ac0 - [-next,v21,14/27] riscv: signal: Add sigcontext save/restore for vector https://git.kernel.org/riscv/c/8ee0b41898fa - [-next,v21,15/27] riscv: signal: Report signal frame size to userspace via auxv https://git.kernel.org/riscv/c/e92f469b0771 - [-next,v21,16/27] riscv: signal: validate altstack to reflect Vector https://git.kernel.org/riscv/c/76e22fdc2c26 - [-next,v21,17/27] riscv: prevent stack corruption by reserving task_pt_regs(p) early https://git.kernel.org/riscv/c/c7cdd96eca28 - [-next,v21,18/27] riscv: kvm: Add V extension to KVM ISA https://git.kernel.org/riscv/c/bf78f1ea6e51 - [-next,v21,19/27] riscv: KVM: Add vector lazy save/restore support https://git.kernel.org/riscv/c/0f4b82579716 - [-next,v21,20/27] riscv: hwcap: change ELF_HWCAP to a function https://git.kernel.org/riscv/c/50724efcb370 - [-next,v21,21/27] riscv: Add prctl controls for userspace vector management https://git.kernel.org/riscv/c/1fd96a3e9d5d - [-next,v21,22/27] riscv: Add sysctl to set the default vector rule for new processes https://git.kernel.org/riscv/c/7ca7a7b9b635 - [-next,v21,23/27] riscv: detect assembler support for .option arch https://git.kernel.org/riscv/c/e4bb020f3dbb - [-next,v21,24/27] riscv: Enable Vector code to be built https://git.kernel.org/riscv/c/fa8e7cce55da - [-next,v21,25/27] riscv: Add documentation for Vector https://git.kernel.org/riscv/c/04a4722eeede - [-next,v21,26/27] selftests: Test RISC-V Vector prctl interface https://git.kernel.org/riscv/c/7cf6198ce22d - [-next,v21,27/27] selftests: add .gitignore file for RISC-V hwprobe https://git.kernel.org/riscv/c/1e72695137ef You are awesome, thank you!
This is the v21 patch series for adding Vector extension support in Linux. Please refer to [1] for the introduction of the patchset. The v21 patch series was aimed to solve build issues from v19, provide usage guideline for the prctl interface, and address review comments on v20. Thank every one who has been reviewing, suggesting on the topic. Hope this get a step closer to the final merge. Here points out where changes are located: Updated patches: 10, 11, 21, 25 New patches: 20 Unchanged patches: 1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 26, 27 Source tree: https://github.com/sifive/riscv-linux/tree/riscv/for-next/vector-v21 Links: - [1] https://lore.kernel.org/all/20230518161949.11203-1-andy.chiu@sifive.com/ --- Changelog V21 - Add usage guideline for the prctl interface (Rémi, patch 25) - Properly define macros to prevent build fails (Björn, patch 21) - expose ELF_HWCAP as a function so we can set bits individually for processes. (patch 20) - Turn off V in ELF_HWCAP when user is not allowed to use it. (Rémi, patch 21) - Send SIGBUS to indicate the allocation for V context fails. (Darius, patch 11) - Refine checks in riscv_v_first_use_handler(). (patch 11, 21) - Refine location of callsite to disable Vector when forked (patch 10) Changelog V20 - Add .gitignore into hwprobe (patch 26) - Implement test for prctl and fix issues (patch 20, 25) - Fix compile error with allmodconfig (patch 20). - Check elf_hwcap in first-use trap (patch 11). - Refine code (patch 11, 20, 21, 23, 24) - Properly add V entry into hwprobe (patch 3). - Fix typos (patch 3, 24) - Use "_unlikely" to detect V since there is no public available hw that supports it (patch 2). Changelog V19 - Rebase to the latest -next branch (at 6.4-rc1 ac9a786). Solve conflicts at patch 14, 15, and 19. - Add a sysctl, and prctl intefaces for userspace Vector control, and a document for it. (patch 20, 21, 24) - Add a Kconfig RISCV_V_DISABLE to set the default value of userspace Vector enablement status at compile-time. (patch 23) - Allow hwprobe interface to probe Vector. (patch 3) - Fix typos and commit msg at patch 6 and 8. Changelog V18 - Rebase to the latest -next branch (at 9c2598d) - patch 7: Detect inconsistent VLEN setup on an SMP system (Heiko). - patch 10: Add blank lines (Heiko) - patch 10: Return immediately in insn_is_vector() if an insn matches (Heiko) - patch 11: Use sizeof(vstate->datap) instead of sizeof(void*) (Eike) Changelog V17 - Rebase to the latest -next branch (at e45d6a5): - Solve conflicts at 9 and 13 due to generic entry - Use generic entry in do_trap_insn_illegal() trap handler Changelog V16 - Rebase to the latest for-next (at 4b74077): - Solve conflicts at 7, and 17 - Use as-instr to detect if assembler supports .option arch directive and remove dependency from GAS, for both ZBB and V. - Cleanup code in KVM vector - Address issue reported by sparse - Refine code: - Fix a mixed-use of space/tab - Remove new lines at the end of file Changelog V15 - Rebase to risc-v -next (v6.3-rc1) - Make V depend on FD in Kconfig according to the spec and shut off v properly. - Fix a syntax error for clang build. But mark RISCV_ISA_V GAS only due to https://reviews.llvm.org/D123515 - Use scratch reg in inline asm instead of t4. - Refine code. - Cleanup per-patch changelogs. Changelog V14 - Rebase to risc-v -next (v6.2-rc7) - Use TOOLCHAIN_HAS_V to detect if we can enable Vector. And refine KBUILD_CFLAGS to remove v from default compile option. - Drop illegal instruction handling patch in kvm and leave it to a independent series[3]. The series has merged into 6.3-rc1 - Move KVM_RISCV_ISA_EXT_V to the end of enum to prevent potential ABI breaks. - Use PT_SIZE_ON_STACK instead of PT_SIZE to fit alignment. Also, remove panic log from v13 (15/19) because it is no longer relevant. - Rewrite insn_is_vector for better structuring (change if-else chain to a switch) - Fix compilation error in the middle of the series - Validate size of the alternative signal frame if V is enabled whenever: - The user call sigaltstack to update altstack - A signal is being delivered - Rename __riscv_v_state to __riscv_v_ext_state. - Add riscv_v_ prefix and rename rvv appropriately - Organize riscv_v_vsize setup code into vector.c - Address the issue mentioned by Heiko on !FPU case - Honor orignal authors that got changed accidentally in v13 4,5,6 Changelog V13 - Rebase to latest risc-v next (v6.2-rc1) - vineetg: Re-organize the series to comply with bisect-ability - andy.chiu: Improve task switch with inline assembly - Re-structure the signal frame to avoid user ABI break. - Implemnt first-use trap and drop prctl for per-task V state enablement. Also, redirect this trap from hs to vs for kvm setup. - Do not expose V context in ptrace/sigframe until the task start using V. But still reserve V context for size ofsigframe reported by auxv. - Drop the kernel mode vector and leave it to another (future) series. Changelog V12 (Chris) - rebases to some point after v5.18-rc6 - add prctl to control per-process V state Chnagelog V10 - Rebase to v5.18-rc6 - Merge several patches - Refine codes - Fix bugs - Add kvm vector support Changelog V9 - Rebase to v5.15 - Merge several patches - Refine codes - Fix a kernel panic issue Changelog V8 - Rebase to v5.14 - Refine struct __riscv_v_ext_state with struct __riscv_ctx_hdr - Refine has_vector into a static key - Defined __reserved space in struct sigcontext for vector and future extensions Changelog V7 - Add support for kernel mode vector - Add vector extension XOR implementation - Optimize task switch codes of vector - Allocate space for vector registers in start_thread() - Fix an illegal instruction exception when accessing vlenb - Optimize vector registers initialization - Initialize vector registers with proper vsetvli then it can work normally - Refine ptrace porting due to generic API changed - Code clean up Changelog V6 - Replace vle.v/vse.v instructions with vle8.v/vse8.v based on 0.9 spec - Add comments based on mailinglist feedback - Fix rv32 build error Changelog V5 - Using regset_size() correctly in generic ptrace - Fix the ptrace porting - Fix compile warning Changelog V4 - Support dynamic vlen - Fix bugs: lazy save/resotre, not saving vtype - Update VS bit offset based on latest vector spec - Add new vector csr based on latest vector spec - Code refine and removed unused macros Changelog V3 - Rebase linux-5.6-rc3 and tested with qemu - Seperate patches with Anup's advice - Give out a ABI puzzle with unlimited vlen Changelog V2 - Fixup typo "vecotr, fstate_save->vstate_save". - Fixup wrong saved registers' length in vector.S. - Seperate unrelated patches from this one. Andy Chiu (11): riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 riscv: Allocate user's vector context in the first-use trap riscv: signal: check fp-reserved words unconditionally riscv: signal: validate altstack to reflect Vector riscv: hwcap: change ELF_HWCAP to a function riscv: Add prctl controls for userspace vector management riscv: Add sysctl to set the default vector rule for new processes riscv: detect assembler support for .option arch riscv: Add documentation for Vector selftests: Test RISC-V Vector prctl interface selftests: add .gitignore file for RISC-V hwprobe Greentime Hu (9): riscv: Add new csr defines related to vector extension riscv: Clear vector regfile on bootup riscv: Introduce Vector enable/disable helpers riscv: Introduce riscv_v_vsize to record size of Vector context riscv: Introduce struct/helpers to save/restore per-task Vector state riscv: Add task switch support for vector riscv: Add ptrace vector support riscv: signal: Add sigcontext save/restore for vector riscv: prevent stack corruption by reserving task_pt_regs(p) early Guo Ren (4): riscv: Rename __switch_to_aux() -> fpu riscv: Extending cpufeature.c to detect V-extension riscv: Disable Vector Instructions for kernel itself riscv: Enable Vector code to be built Vincent Chen (3): riscv: signal: Report signal frame size to userspace via auxv riscv: kvm: Add V extension to KVM ISA riscv: KVM: Add vector lazy save/restore support Documentation/riscv/hwprobe.rst | 3 + Documentation/riscv/index.rst | 1 + Documentation/riscv/vector.rst | 132 +++++++++ arch/riscv/Kconfig | 39 ++- arch/riscv/Makefile | 6 +- arch/riscv/include/asm/csr.h | 18 +- arch/riscv/include/asm/elf.h | 11 +- arch/riscv/include/asm/hwcap.h | 3 + arch/riscv/include/asm/insn.h | 29 ++ arch/riscv/include/asm/kvm_host.h | 2 + arch/riscv/include/asm/kvm_vcpu_vector.h | 82 ++++++ arch/riscv/include/asm/processor.h | 13 + arch/riscv/include/asm/switch_to.h | 9 +- arch/riscv/include/asm/thread_info.h | 3 + arch/riscv/include/asm/vector.h | 184 ++++++++++++ arch/riscv/include/uapi/asm/auxvec.h | 1 + arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/include/uapi/asm/kvm.h | 8 + arch/riscv/include/uapi/asm/ptrace.h | 39 +++ arch/riscv/include/uapi/asm/sigcontext.h | 16 +- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpufeature.c | 25 ++ arch/riscv/kernel/entry.S | 6 +- arch/riscv/kernel/head.S | 41 ++- arch/riscv/kernel/process.c | 20 ++ arch/riscv/kernel/ptrace.c | 70 +++++ arch/riscv/kernel/setup.c | 3 + arch/riscv/kernel/signal.c | 220 ++++++++++++-- arch/riscv/kernel/smpboot.c | 7 + arch/riscv/kernel/sys_riscv.c | 4 + arch/riscv/kernel/traps.c | 26 +- arch/riscv/kernel/vector.c | 276 ++++++++++++++++++ arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 25 ++ arch/riscv/kvm/vcpu_vector.c | 186 ++++++++++++ include/uapi/linux/elf.h | 1 + include/uapi/linux/prctl.h | 11 + kernel/sys.c | 12 + tools/testing/selftests/riscv/Makefile | 2 +- .../selftests/riscv/hwprobe/.gitignore | 1 + .../testing/selftests/riscv/vector/.gitignore | 2 + tools/testing/selftests/riscv/vector/Makefile | 15 + .../riscv/vector/vstate_exec_nolibc.c | 111 +++++++ .../selftests/riscv/vector/vstate_prctl.c | 189 ++++++++++++ 45 files changed, 1805 insertions(+), 51 deletions(-) create mode 100644 Documentation/riscv/vector.rst create mode 100644 arch/riscv/include/asm/kvm_vcpu_vector.h create mode 100644 arch/riscv/include/asm/vector.h create mode 100644 arch/riscv/kernel/vector.c create mode 100644 arch/riscv/kvm/vcpu_vector.c create mode 100644 tools/testing/selftests/riscv/hwprobe/.gitignore create mode 100644 tools/testing/selftests/riscv/vector/.gitignore create mode 100644 tools/testing/selftests/riscv/vector/Makefile create mode 100644 tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c create mode 100644 tools/testing/selftests/riscv/vector/vstate_prctl.c