| Message ID | 20230602181450.1151368-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/i915/display: Extract display init from intel_device_info_runtime_init | expand |
On Fri, 02 Jun 2023, Matt Roper <matthew.d.roper@intel.com> wrote: > Moving display-specific runtime info initialization into display/ makes > the display code more self-contained and also makes it easier to call > from the Xe driver. > > v2: > - Drop unnecessary display/ prefix from #includes. (Jani) > - Clear runtime info if fusing leaves no pipes remaining, the same as > we do when fusing indicates the entire display controller is > unavailable. (Jani) > - Move adjustment of DRIVER_MODESET / DRIVER_ATOMIC after call to > intel_display_device_info_runtime_init(); HAS_DISPLAY may have > changed to false during the runtime init. (Jani) > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > .../drm/i915/display/intel_display_device.c | 127 +++++++++++++++ > .../drm/i915/display/intel_display_device.h | 1 + > drivers/gpu/drm/i915/intel_device_info.c | 154 ++---------------- > 3 files changed, 144 insertions(+), 138 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c > index 464df1764a86..967bac29b5d5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -9,6 +9,8 @@ > > #include "i915_drv.h" > #include "i915_reg.h" > +#include "intel_de.h" > +#include "intel_display.h" > #include "intel_display_device.h" > #include "intel_display_power.h" > #include "intel_display_reg_defs.h" > @@ -778,3 +780,128 @@ intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid, > > return &no_display; > } > + > +void intel_display_device_info_runtime_init(struct drm_i915_private *i915) > +{ > + struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915); > + enum pipe pipe; > + > + /* Wa_14011765242: adl-s A0,A1 */ > + if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2)) > + for_each_pipe(i915, pipe) > + display_runtime->num_scalers[pipe] = 0; > + else if (DISPLAY_VER(i915) >= 11) { > + for_each_pipe(i915, pipe) > + display_runtime->num_scalers[pipe] = 2; > + } else if (DISPLAY_VER(i915) >= 9) { > + display_runtime->num_scalers[PIPE_A] = 2; > + display_runtime->num_scalers[PIPE_B] = 2; > + display_runtime->num_scalers[PIPE_C] = 1; > + } > + > + if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) > + for_each_pipe(i915, pipe) > + display_runtime->num_sprites[pipe] = 4; > + else if (DISPLAY_VER(i915) >= 11) > + for_each_pipe(i915, pipe) > + display_runtime->num_sprites[pipe] = 6; > + else if (DISPLAY_VER(i915) == 10) > + for_each_pipe(i915, pipe) > + display_runtime->num_sprites[pipe] = 3; > + else if (IS_BROXTON(i915)) { > + /* > + * Skylake and Broxton currently don't expose the topmost plane as its > + * use is exclusive with the legacy cursor and we only want to expose > + * one of those, not both. Until we can safely expose the topmost plane > + * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, > + * we don't expose the topmost plane at all to prevent ABI breakage > + * down the line. > + */ > + > + display_runtime->num_sprites[PIPE_A] = 2; > + display_runtime->num_sprites[PIPE_B] = 2; > + display_runtime->num_sprites[PIPE_C] = 1; > + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > + for_each_pipe(i915, pipe) > + display_runtime->num_sprites[pipe] = 2; > + } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) { > + for_each_pipe(i915, pipe) > + display_runtime->num_sprites[pipe] = 1; > + } > + > + if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) && > + !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) { > + drm_info(&i915->drm, "Display not present, disabling\n"); > + goto display_fused_off; > + } > + > + if (IS_GRAPHICS_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) { > + u32 fuse_strap = intel_de_read(i915, FUSE_STRAP); > + u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP); > + > + /* > + * SFUSE_STRAP is supposed to have a bit signalling the display > + * is fused off. Unfortunately it seems that, at least in > + * certain cases, fused off display means that PCH display > + * reads don't land anywhere. In that case, we read 0s. > + * > + * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK > + * should be set when taking over after the firmware. > + */ > + if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || > + sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || > + (HAS_PCH_CPT(i915) && > + !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { > + drm_info(&i915->drm, > + "Display fused off, disabling\n"); > + goto display_fused_off; > + } else if (fuse_strap & IVB_PIPE_C_DISABLE) { > + drm_info(&i915->drm, "PipeC fused off\n"); > + display_runtime->pipe_mask &= ~BIT(PIPE_C); > + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); > + } > + } else if (DISPLAY_VER(i915) >= 9) { > + u32 dfsm = intel_de_read(i915, SKL_DFSM); > + > + if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { > + display_runtime->pipe_mask &= ~BIT(PIPE_A); > + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); > + display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); > + } > + if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { > + display_runtime->pipe_mask &= ~BIT(PIPE_B); > + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); > + } > + if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { > + display_runtime->pipe_mask &= ~BIT(PIPE_C); > + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); > + } > + > + if (DISPLAY_VER(i915) >= 12 && > + (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { > + display_runtime->pipe_mask &= ~BIT(PIPE_D); > + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); > + } > + > + if (!display_runtime->pipe_mask) > + goto display_fused_off; > + > + if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) > + display_runtime->has_hdcp = 0; > + > + if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) > + display_runtime->fbc_mask = 0; > + > + if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) > + display_runtime->has_dmc = 0; > + > + if (IS_DISPLAY_VER(i915, 10, 12) && > + (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) > + display_runtime->has_dsc = 0; > + } > + > + return; > + > +display_fused_off: > + memset(display_runtime, 0, sizeof(*display_runtime)); > +} > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h > index 2aa82cbdf1c5..4f931258d81d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.h > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h > @@ -124,5 +124,6 @@ struct intel_display_device_info { > const struct intel_display_device_info * > intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid, > u16 *ver, u16 *rel, u16 *step); > +void intel_display_device_info_runtime_init(struct drm_i915_private *i915); > > #endif > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 2f79d232b04a..6e49caf241a5 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -27,9 +27,7 @@ > #include <drm/drm_print.h> > #include <drm/i915_pciids.h> > > -#include "display/intel_cdclk.h" > -#include "display/intel_de.h" > -#include "display/intel_display.h" > +#include "display/intel_display_device.h" > #include "gt/intel_gt_regs.h" > #include "i915_drv.h" > #include "i915_reg.h" > @@ -411,153 +409,33 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > { > struct intel_device_info *info = mkwrite_device_info(dev_priv); > struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); > - struct intel_display_runtime_info *display_runtime = > - DISPLAY_RUNTIME_INFO(dev_priv); > - enum pipe pipe; > > - /* Wa_14011765242: adl-s A0,A1 */ > - if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2)) > - for_each_pipe(dev_priv, pipe) > - display_runtime->num_scalers[pipe] = 0; > - else if (DISPLAY_VER(dev_priv) >= 11) { > - for_each_pipe(dev_priv, pipe) > - display_runtime->num_scalers[pipe] = 2; > - } else if (DISPLAY_VER(dev_priv) >= 9) { > - display_runtime->num_scalers[PIPE_A] = 2; > - display_runtime->num_scalers[PIPE_B] = 2; > - display_runtime->num_scalers[PIPE_C] = 1; > - } > - > - BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); > - > - if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) > - for_each_pipe(dev_priv, pipe) > - display_runtime->num_sprites[pipe] = 4; > - else if (DISPLAY_VER(dev_priv) >= 11) > - for_each_pipe(dev_priv, pipe) > - display_runtime->num_sprites[pipe] = 6; > - else if (DISPLAY_VER(dev_priv) == 10) > - for_each_pipe(dev_priv, pipe) > - display_runtime->num_sprites[pipe] = 3; > - else if (IS_BROXTON(dev_priv)) { > - /* > - * Skylake and Broxton currently don't expose the topmost plane as its > - * use is exclusive with the legacy cursor and we only want to expose > - * one of those, not both. Until we can safely expose the topmost plane > - * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, > - * we don't expose the topmost plane at all to prevent ABI breakage > - * down the line. > - */ > - > - display_runtime->num_sprites[PIPE_A] = 2; > - display_runtime->num_sprites[PIPE_B] = 2; > - display_runtime->num_sprites[PIPE_C] = 1; > - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > - for_each_pipe(dev_priv, pipe) > - display_runtime->num_sprites[pipe] = 2; > - } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) { > - for_each_pipe(dev_priv, pipe) > - display_runtime->num_sprites[pipe] = 1; > - } > - > - if (HAS_DISPLAY(dev_priv) && > - (IS_DGFX(dev_priv) || DISPLAY_VER(dev_priv) >= 14) && > - !(intel_de_read(dev_priv, GU_CNTL_PROTECTED) & DEPRESENT)) { > - drm_info(&dev_priv->drm, "Display not present, disabling\n"); > - > - display_runtime->pipe_mask = 0; > - } > - > - if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) && > - HAS_PCH_SPLIT(dev_priv)) { > - u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); > - u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); > - > - /* > - * SFUSE_STRAP is supposed to have a bit signalling the display > - * is fused off. Unfortunately it seems that, at least in > - * certain cases, fused off display means that PCH display > - * reads don't land anywhere. In that case, we read 0s. > - * > - * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK > - * should be set when taking over after the firmware. > - */ > - if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || > - sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || > - (HAS_PCH_CPT(dev_priv) && > - !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { > - drm_info(&dev_priv->drm, > - "Display fused off, disabling\n"); > - display_runtime->pipe_mask = 0; > - } else if (fuse_strap & IVB_PIPE_C_DISABLE) { > - drm_info(&dev_priv->drm, "PipeC fused off\n"); > - display_runtime->pipe_mask &= ~BIT(PIPE_C); > - display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); > - } > - } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { > - u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); > - > - if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { > - display_runtime->pipe_mask &= ~BIT(PIPE_A); > - display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); > - display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); > - } > - if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { > - display_runtime->pipe_mask &= ~BIT(PIPE_B); > - display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); > - } > - if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { > - display_runtime->pipe_mask &= ~BIT(PIPE_C); > - display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); > - } > - > - if (DISPLAY_VER(dev_priv) >= 12 && > - (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { > - display_runtime->pipe_mask &= ~BIT(PIPE_D); > - display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); > - } > - > - if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) > - display_runtime->has_hdcp = 0; > - > - if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) > - display_runtime->fbc_mask = 0; > - > - if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) > - display_runtime->has_dmc = 0; > - > - if (IS_DISPLAY_VER(dev_priv, 10, 12) && > - (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) > - display_runtime->has_dsc = 0; > - } > - > - if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { > - drm_info(&dev_priv->drm, > - "Disabling ppGTT for VT-d support\n"); > - runtime->ppgtt_type = INTEL_PPGTT_NONE; > - } > - > - runtime->rawclk_freq = intel_read_rawclk(dev_priv); > - drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); > + if (HAS_DISPLAY(dev_priv)) > + intel_display_device_info_runtime_init(dev_priv); > > + /* Display may have been disabled by runtime init */ > if (!HAS_DISPLAY(dev_priv)) { > dev_priv->drm.driver_features &= ~(DRIVER_MODESET | > DRIVER_ATOMIC); > info->display = &no_display; > - > - display_runtime->cpu_transcoder_mask = 0; > - memset(display_runtime->num_sprites, 0, sizeof(display_runtime->num_sprites)); > - memset(display_runtime->num_scalers, 0, sizeof(display_runtime->num_scalers)); > - display_runtime->fbc_mask = 0; > - display_runtime->has_hdcp = false; > - display_runtime->has_dmc = false; > - display_runtime->has_dsc = false; > } > > /* Disable nuclear pageflip by default on pre-g4x */ > if (!dev_priv->params.nuclear_pageflip && > DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) > dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; > + > + BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); > + > + if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { > + drm_info(&dev_priv->drm, > + "Disabling ppGTT for VT-d support\n"); > + runtime->ppgtt_type = INTEL_PPGTT_NONE; > + } > + > + runtime->rawclk_freq = intel_read_rawclk(dev_priv); > + drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); > + > } > > /*
On Mon, Jun 05, 2023 at 09:14:58AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/display: Extract display init from intel_device_info_runtime_init (rev2) > URL : https://patchwork.freedesktop.org/series/118730/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_13222_full -> Patchwork_118730v2_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_118730v2_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_118730v2_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (7 -> 7) > ------------------------------ > > No changes in participating hosts > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_118730v2_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@kms_busy@extended-modeset-hang-newfb-with-reset@pipe-b: > - shard-snb: [PASS][1] -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-snb2/igt@kms_busy@extended-modeset-hang-newfb-with-reset@pipe-b.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-snb2/igt@kms_busy@extended-modeset-hang-newfb-with-reset@pipe-b.html Random incomplete; no reason in the logs. Does not appear to be related to this patch. Applied to drm-intel-next. Thanks Jani for the review. Matt > > > Known issues > ------------ > > Here are the changes found in Patchwork_118730v2_full that come from known issues: > > ### CI changes ### > > #### Possible fixes #### > > * boot: > - shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#7849] / [i915#8293]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk1/boot.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk2/boot.html > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/boot.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk4/boot.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk4/boot.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk5/boot.html > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk5/boot.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk6/boot.html > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk7/boot.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/boot.html > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk9/boot.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk9/boot.html > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk7/boot.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk7/boot.html > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk7/boot.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk6/boot.html > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk6/boot.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk6/boot.html > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk5/boot.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk5/boot.html > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk4/boot.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk4/boot.html > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk4/boot.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk3/boot.html > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk3/boot.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk3/boot.html > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk2/boot.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk2/boot.html > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk2/boot.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk1/boot.html > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk1/boot.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk1/boot.html > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk9/boot.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk9/boot.html > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk9/boot.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk8/boot.html > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk8/boot.html > > > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_exec_capture@capture-invisible@smem0: > - shard-glk: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#4579] / [i915#6334]) > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk4/igt@gem_exec_capture@capture-invisible@smem0.html > > * igt@gem_exec_fair@basic-none-solo@rcs0: > - shard-apl: [PASS][53] -> [FAIL][54] ([i915#2842]) > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html > > * igt@gem_exec_fair@basic-throttle@rcs0: > - shard-glk: NOTRUN -> [FAIL][55] ([i915#2842]) +1 similar issue > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html > > * igt@gem_lmem_swapping@random: > - shard-glk: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#4613]) +2 similar issues > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk4/igt@gem_lmem_swapping@random.html > > * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a: > - shard-glk: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#1937] / [i915#4579]) > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk8/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html > > * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip: > - shard-apl: NOTRUN -> [SKIP][58] ([fdo#109271]) +47 similar issues > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-apl7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html > > * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs: > - shard-glk: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#3886]) +8 similar issues > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk2/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html > > * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: > - shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#3886]) +2 similar issues > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-apl7/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html > > * igt@kms_cursor_crc@cursor-rapid-movement-32x10: > - shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#4579]) +2 similar issues > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-apl7/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html > > * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1: > - shard-apl: [PASS][62] -> [ABORT][63] ([i915#180]) > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html > > * igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-hdmi-a-1: > - shard-snb: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#4579]) +11 similar issues > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-snb1/igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-hdmi-a-1.html > > * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a-vga-1: > - shard-snb: NOTRUN -> [SKIP][65] ([fdo#109271]) +19 similar issues > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-snb2/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a-vga-1.html > > * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: > - shard-glk: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#658]) +1 similar issue > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk6/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html > > * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area: > - shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#658]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-apl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html > > * igt@kms_scaling_modes@scaling-mode-full: > - shard-glk: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4579]) +7 similar issues > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk2/igt@kms_scaling_modes@scaling-mode-full.html > > * igt@kms_setmode@basic@pipe-a-vga-1: > - shard-snb: NOTRUN -> [FAIL][69] ([i915#5465]) +1 similar issue > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-snb4/igt@kms_setmode@basic@pipe-a-vga-1.html > > * igt@kms_vblank@pipe-d-wait-busy-hang: > - shard-glk: NOTRUN -> [SKIP][70] ([fdo#109271]) +117 similar issues > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk4/igt@kms_vblank@pipe-d-wait-busy-hang.html > > * igt@kms_writeback@writeback-invalid-parameters: > - shard-glk: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2437]) > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk4/igt@kms_writeback@writeback-invalid-parameters.html > > > #### Possible fixes #### > > * igt@drm_fdinfo@most-busy-idle-check-all@rcs0: > - {shard-rkl}: [FAIL][72] ([i915#7742]) -> [PASS][73] > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html > > * igt@gem_eio@hibernate: > - {shard-dg1}: [ABORT][74] ([i915#4391] / [i915#7975] / [i915#8213]) -> [PASS][75] > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-dg1-14/igt@gem_eio@hibernate.html > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-dg1-17/igt@gem_eio@hibernate.html > > * igt@gem_eio@unwedge-stress: > - {shard-dg1}: [FAIL][76] ([i915#5784]) -> [PASS][77] > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-dg1-17/igt@gem_eio@unwedge-stress.html > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-dg1-18/igt@gem_eio@unwedge-stress.html > > * igt@gem_exec_fair@basic-pace-share@rcs0: > - shard-glk: [FAIL][78] ([i915#2842]) -> [PASS][79] > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html > > * igt@gem_exec_suspend@basic-s4-devices@lmem0: > - {shard-dg1}: [ABORT][80] ([i915#7975] / [i915#8213]) -> [PASS][81] > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-dg1-17/igt@gem_exec_suspend@basic-s4-devices@lmem0.html > > * igt@gem_exec_suspend@basic-s4-devices@smem: > - {shard-tglu}: [ABORT][82] ([i915#7975] / [i915#8213]) -> [PASS][83] > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-tglu-9/igt@gem_exec_suspend@basic-s4-devices@smem.html > > * igt@gen9_exec_parse@allowed-all: > - shard-apl: [ABORT][84] ([i915#5566]) -> [PASS][85] > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-apl3/igt@gen9_exec_parse@allowed-all.html > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-apl7/igt@gen9_exec_parse@allowed-all.html > - shard-glk: [ABORT][86] ([i915#5566]) -> [PASS][87] > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/igt@gen9_exec_parse@allowed-all.html > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk2/igt@gen9_exec_parse@allowed-all.html > > * igt@i915_pm_rpm@dpms-lpsp: > - {shard-rkl}: [SKIP][88] ([i915#1397]) -> [PASS][89] > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-rkl-4/igt@i915_pm_rpm@dpms-lpsp.html > [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-rkl-7/igt@i915_pm_rpm@dpms-lpsp.html > > * igt@kms_cursor_legacy@cursor-vs-flip-legacy: > - shard-glk: [FAIL][90] -> [PASS][91] > [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html > [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk7/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html > > * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: > - shard-glk: [FAIL][92] ([i915#2346]) -> [PASS][93] > [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html > [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html > > * igt@kms_flip@flip-vs-suspend@b-dp1: > - shard-apl: [ABORT][94] ([i915#180]) -> [PASS][95] > [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-apl6/igt@kms_flip@flip-vs-suspend@b-dp1.html > [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-apl1/igt@kms_flip@flip-vs-suspend@b-dp1.html > > > #### Warnings #### > > * igt@kms_hdmi_inject@inject-audio: > - shard-snb: [FAIL][96] ([IGT#3]) -> [SKIP][97] ([fdo#109271]) > [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13222/shard-snb7/igt@kms_hdmi_inject@inject-audio.html > [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/shard-snb5/igt@kms_hdmi_inject@inject-audio.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 > [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3 > [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 > [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 > [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 > [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 > [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 > [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 > [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937 > [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 > [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 > [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 > [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 > [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 > [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 > [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 > [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 > [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 > [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 > [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 > [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 > [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 > [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 > [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 > [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 > [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 > [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 > [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 > [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 > [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 > [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 > [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989 > [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 > [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 > [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 > [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 > [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 > [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 > [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 > [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 > [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 > [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 > [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 > [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 > [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 > [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 > [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 > [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 > [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 > [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 > [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 > [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 > [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465 > [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 > [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 > [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 > [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334 > [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461 > [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 > [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 > [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 > [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 > [i915#7849]: https://gitlab.freedesktop.org/drm/intel/issues/7849 > [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975 > [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213 > [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293 > [i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398 > [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414 > [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555 > > > Build changes > ------------- > > * Linux: CI_DRM_13222 -> Patchwork_118730v2 > > CI-20190529: 20190529 > CI_DRM_13222: 9f99072561664a4b16520f460ddf583c1c0be7d4 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_7318: c2d8ef8b9397d0976959f29dc1dd7c8a698d65fe @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_118730v2: 9f99072561664a4b16520f460ddf583c1c0be7d4 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118730v2/index.html
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 464df1764a86..967bac29b5d5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -9,6 +9,8 @@ #include "i915_drv.h" #include "i915_reg.h" +#include "intel_de.h" +#include "intel_display.h" #include "intel_display_device.h" #include "intel_display_power.h" #include "intel_display_reg_defs.h" @@ -778,3 +780,128 @@ intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid, return &no_display; } + +void intel_display_device_info_runtime_init(struct drm_i915_private *i915) +{ + struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915); + enum pipe pipe; + + /* Wa_14011765242: adl-s A0,A1 */ + if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2)) + for_each_pipe(i915, pipe) + display_runtime->num_scalers[pipe] = 0; + else if (DISPLAY_VER(i915) >= 11) { + for_each_pipe(i915, pipe) + display_runtime->num_scalers[pipe] = 2; + } else if (DISPLAY_VER(i915) >= 9) { + display_runtime->num_scalers[PIPE_A] = 2; + display_runtime->num_scalers[PIPE_B] = 2; + display_runtime->num_scalers[PIPE_C] = 1; + } + + if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) + for_each_pipe(i915, pipe) + display_runtime->num_sprites[pipe] = 4; + else if (DISPLAY_VER(i915) >= 11) + for_each_pipe(i915, pipe) + display_runtime->num_sprites[pipe] = 6; + else if (DISPLAY_VER(i915) == 10) + for_each_pipe(i915, pipe) + display_runtime->num_sprites[pipe] = 3; + else if (IS_BROXTON(i915)) { + /* + * Skylake and Broxton currently don't expose the topmost plane as its + * use is exclusive with the legacy cursor and we only want to expose + * one of those, not both. Until we can safely expose the topmost plane + * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, + * we don't expose the topmost plane at all to prevent ABI breakage + * down the line. + */ + + display_runtime->num_sprites[PIPE_A] = 2; + display_runtime->num_sprites[PIPE_B] = 2; + display_runtime->num_sprites[PIPE_C] = 1; + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { + for_each_pipe(i915, pipe) + display_runtime->num_sprites[pipe] = 2; + } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) { + for_each_pipe(i915, pipe) + display_runtime->num_sprites[pipe] = 1; + } + + if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) && + !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) { + drm_info(&i915->drm, "Display not present, disabling\n"); + goto display_fused_off; + } + + if (IS_GRAPHICS_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) { + u32 fuse_strap = intel_de_read(i915, FUSE_STRAP); + u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP); + + /* + * SFUSE_STRAP is supposed to have a bit signalling the display + * is fused off. Unfortunately it seems that, at least in + * certain cases, fused off display means that PCH display + * reads don't land anywhere. In that case, we read 0s. + * + * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK + * should be set when taking over after the firmware. + */ + if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || + sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || + (HAS_PCH_CPT(i915) && + !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { + drm_info(&i915->drm, + "Display fused off, disabling\n"); + goto display_fused_off; + } else if (fuse_strap & IVB_PIPE_C_DISABLE) { + drm_info(&i915->drm, "PipeC fused off\n"); + display_runtime->pipe_mask &= ~BIT(PIPE_C); + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); + } + } else if (DISPLAY_VER(i915) >= 9) { + u32 dfsm = intel_de_read(i915, SKL_DFSM); + + if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { + display_runtime->pipe_mask &= ~BIT(PIPE_A); + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); + display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); + } + if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { + display_runtime->pipe_mask &= ~BIT(PIPE_B); + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); + } + if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { + display_runtime->pipe_mask &= ~BIT(PIPE_C); + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); + } + + if (DISPLAY_VER(i915) >= 12 && + (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { + display_runtime->pipe_mask &= ~BIT(PIPE_D); + display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); + } + + if (!display_runtime->pipe_mask) + goto display_fused_off; + + if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) + display_runtime->has_hdcp = 0; + + if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) + display_runtime->fbc_mask = 0; + + if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) + display_runtime->has_dmc = 0; + + if (IS_DISPLAY_VER(i915, 10, 12) && + (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) + display_runtime->has_dsc = 0; + } + + return; + +display_fused_off: + memset(display_runtime, 0, sizeof(*display_runtime)); +} diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 2aa82cbdf1c5..4f931258d81d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -124,5 +124,6 @@ struct intel_display_device_info { const struct intel_display_device_info * intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid, u16 *ver, u16 *rel, u16 *step); +void intel_display_device_info_runtime_init(struct drm_i915_private *i915); #endif diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 2f79d232b04a..6e49caf241a5 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -27,9 +27,7 @@ #include <drm/drm_print.h> #include <drm/i915_pciids.h> -#include "display/intel_cdclk.h" -#include "display/intel_de.h" -#include "display/intel_display.h" +#include "display/intel_display_device.h" #include "gt/intel_gt_regs.h" #include "i915_drv.h" #include "i915_reg.h" @@ -411,153 +409,33 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) { struct intel_device_info *info = mkwrite_device_info(dev_priv); struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); - struct intel_display_runtime_info *display_runtime = - DISPLAY_RUNTIME_INFO(dev_priv); - enum pipe pipe; - /* Wa_14011765242: adl-s A0,A1 */ - if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2)) - for_each_pipe(dev_priv, pipe) - display_runtime->num_scalers[pipe] = 0; - else if (DISPLAY_VER(dev_priv) >= 11) { - for_each_pipe(dev_priv, pipe) - display_runtime->num_scalers[pipe] = 2; - } else if (DISPLAY_VER(dev_priv) >= 9) { - display_runtime->num_scalers[PIPE_A] = 2; - display_runtime->num_scalers[PIPE_B] = 2; - display_runtime->num_scalers[PIPE_C] = 1; - } - - BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); - - if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) - for_each_pipe(dev_priv, pipe) - display_runtime->num_sprites[pipe] = 4; - else if (DISPLAY_VER(dev_priv) >= 11) - for_each_pipe(dev_priv, pipe) - display_runtime->num_sprites[pipe] = 6; - else if (DISPLAY_VER(dev_priv) == 10) - for_each_pipe(dev_priv, pipe) - display_runtime->num_sprites[pipe] = 3; - else if (IS_BROXTON(dev_priv)) { - /* - * Skylake and Broxton currently don't expose the topmost plane as its - * use is exclusive with the legacy cursor and we only want to expose - * one of those, not both. Until we can safely expose the topmost plane - * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, - * we don't expose the topmost plane at all to prevent ABI breakage - * down the line. - */ - - display_runtime->num_sprites[PIPE_A] = 2; - display_runtime->num_sprites[PIPE_B] = 2; - display_runtime->num_sprites[PIPE_C] = 1; - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - for_each_pipe(dev_priv, pipe) - display_runtime->num_sprites[pipe] = 2; - } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) { - for_each_pipe(dev_priv, pipe) - display_runtime->num_sprites[pipe] = 1; - } - - if (HAS_DISPLAY(dev_priv) && - (IS_DGFX(dev_priv) || DISPLAY_VER(dev_priv) >= 14) && - !(intel_de_read(dev_priv, GU_CNTL_PROTECTED) & DEPRESENT)) { - drm_info(&dev_priv->drm, "Display not present, disabling\n"); - - display_runtime->pipe_mask = 0; - } - - if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) && - HAS_PCH_SPLIT(dev_priv)) { - u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); - u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); - - /* - * SFUSE_STRAP is supposed to have a bit signalling the display - * is fused off. Unfortunately it seems that, at least in - * certain cases, fused off display means that PCH display - * reads don't land anywhere. In that case, we read 0s. - * - * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK - * should be set when taking over after the firmware. - */ - if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || - sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || - (HAS_PCH_CPT(dev_priv) && - !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { - drm_info(&dev_priv->drm, - "Display fused off, disabling\n"); - display_runtime->pipe_mask = 0; - } else if (fuse_strap & IVB_PIPE_C_DISABLE) { - drm_info(&dev_priv->drm, "PipeC fused off\n"); - display_runtime->pipe_mask &= ~BIT(PIPE_C); - display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); - } - } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { - u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); - - if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { - display_runtime->pipe_mask &= ~BIT(PIPE_A); - display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); - display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); - } - if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { - display_runtime->pipe_mask &= ~BIT(PIPE_B); - display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); - } - if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { - display_runtime->pipe_mask &= ~BIT(PIPE_C); - display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); - } - - if (DISPLAY_VER(dev_priv) >= 12 && - (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { - display_runtime->pipe_mask &= ~BIT(PIPE_D); - display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); - } - - if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) - display_runtime->has_hdcp = 0; - - if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) - display_runtime->fbc_mask = 0; - - if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) - display_runtime->has_dmc = 0; - - if (IS_DISPLAY_VER(dev_priv, 10, 12) && - (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) - display_runtime->has_dsc = 0; - } - - if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { - drm_info(&dev_priv->drm, - "Disabling ppGTT for VT-d support\n"); - runtime->ppgtt_type = INTEL_PPGTT_NONE; - } - - runtime->rawclk_freq = intel_read_rawclk(dev_priv); - drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); + if (HAS_DISPLAY(dev_priv)) + intel_display_device_info_runtime_init(dev_priv); + /* Display may have been disabled by runtime init */ if (!HAS_DISPLAY(dev_priv)) { dev_priv->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); info->display = &no_display; - - display_runtime->cpu_transcoder_mask = 0; - memset(display_runtime->num_sprites, 0, sizeof(display_runtime->num_sprites)); - memset(display_runtime->num_scalers, 0, sizeof(display_runtime->num_scalers)); - display_runtime->fbc_mask = 0; - display_runtime->has_hdcp = false; - display_runtime->has_dmc = false; - display_runtime->has_dsc = false; } /* Disable nuclear pageflip by default on pre-g4x */ if (!dev_priv->params.nuclear_pageflip && DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; + + BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); + + if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { + drm_info(&dev_priv->drm, + "Disabling ppGTT for VT-d support\n"); + runtime->ppgtt_type = INTEL_PPGTT_NONE; + } + + runtime->rawclk_freq = intel_read_rawclk(dev_priv); + drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); + } /*
Moving display-specific runtime info initialization into display/ makes the display code more self-contained and also makes it easier to call from the Xe driver. v2: - Drop unnecessary display/ prefix from #includes. (Jani) - Clear runtime info if fusing leaves no pipes remaining, the same as we do when fusing indicates the entire display controller is unavailable. (Jani) - Move adjustment of DRIVER_MODESET / DRIVER_ATOMIC after call to intel_display_device_info_runtime_init(); HAS_DISPLAY may have changed to false during the runtime init. (Jani) Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- .../drm/i915/display/intel_display_device.c | 127 +++++++++++++++ .../drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/intel_device_info.c | 154 ++---------------- 3 files changed, 144 insertions(+), 138 deletions(-)