| Message ID | 1685982557-28326-9-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add devicetree support for SDX75 Modem and IDP | expand |
On 5.06.2023 18:29, Rohit Agarwal wrote: > Add the debug uart console node in devicetree. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > index f83eef8..47170ae 100644 > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > @@ -385,6 +385,34 @@ > #power-domain-cells = <1>; > }; > > + qupv3_id_0: geniqup@9c0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x009c0000 0x0 0x2000>; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + clock-names = "m-ahb", > + "s-ahb"; > + iommus = <&apps_smmu 0xe3 0x0>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + uart1: serial@984000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0x0 0x00984000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; > + pinctrl-0 = <&qupv3_se1_2uart_tx_active>, > + <&qupv3_se1_2uart_rx_active>; > + pinctrl-1 = <&qupv3_se1_2uart_sleep>; > + pinctrl-names = "default", > + "sleep"; > + status = "disabled"; > + }; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x40000>; > @@ -413,6 +441,27 @@ > interrupt-controller; > #interrupt-cells = <2>; > wakeup-parent = <&pdc>; > + > + qupv3_se1_2uart_tx_active: qupv3-se1-2uart-tx-active-state { > + pins = "gpio12"; > + function = "qup_se1_l2_mira"; > + drive-strength= <2>; > + bias-disable; > + }; You can bunch these two up like this: qupv3_se1_2uart_active: qup.... { tx { pins = ... foo = ... }; rx { pins = ... bar = ... }; }; Konrad > + > + qupv3_se1_2uart_rx_active: qupv3-se1-2uart-rx-active-state { > + pins = "gpio13"; > + function = "qup_se1_l3_mira"; > + drive-strength= <2>; > + bias-disable; > + }; > + > + qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { > + pins = "gpio12", "gpio13"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > }; > > apps_smmu: iommu@15000000 {
On 05/06/2023 18:29, Rohit Agarwal wrote: > Add the debug uart console node in devicetree. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+) GCC and UART are parts of basic DTSI and do not make sense on their own. Otherwise, what exactly boots on your "basic DTSI" commit if you do not have any clocks and serial console? Best regards, Krzysztof
On 6/6/2023 11:36 AM, Krzysztof Kozlowski wrote: > On 05/06/2023 18:29, Rohit Agarwal wrote: >> Add the debug uart console node in devicetree. >> >> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 49 insertions(+) > GCC and UART are parts of basic DTSI and do not make sense on their own. > Otherwise, what exactly boots on your "basic DTSI" commit if you do not > have any clocks and serial console? Ok Will club all the additional patches into the same base dtsi patch. Thanks, Rohit. > > Best regards, > Krzysztof >
On 6/5/2023 11:47 PM, Konrad Dybcio wrote: > > On 5.06.2023 18:29, Rohit Agarwal wrote: >> Add the debug uart console node in devicetree. >> >> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 49 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi >> index f83eef8..47170ae 100644 >> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi >> @@ -385,6 +385,34 @@ >> #power-domain-cells = <1>; >> }; >> >> + qupv3_id_0: geniqup@9c0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0x0 0x009c0000 0x0 0x2000>; >> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >> + clock-names = "m-ahb", >> + "s-ahb"; >> + iommus = <&apps_smmu 0xe3 0x0>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + status = "disabled"; >> + >> + uart1: serial@984000 { >> + compatible = "qcom,geni-debug-uart"; >> + reg = <0x0 0x00984000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >> + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; >> + pinctrl-0 = <&qupv3_se1_2uart_tx_active>, >> + <&qupv3_se1_2uart_rx_active>; >> + pinctrl-1 = <&qupv3_se1_2uart_sleep>; >> + pinctrl-names = "default", >> + "sleep"; >> + status = "disabled"; >> + }; >> + }; >> + >> tcsr_mutex: hwlock@1f40000 { >> compatible = "qcom,tcsr-mutex"; >> reg = <0x0 0x01f40000 0x0 0x40000>; >> @@ -413,6 +441,27 @@ >> interrupt-controller; >> #interrupt-cells = <2>; >> wakeup-parent = <&pdc>; >> + >> + qupv3_se1_2uart_tx_active: qupv3-se1-2uart-tx-active-state { >> + pins = "gpio12"; >> + function = "qup_se1_l2_mira"; >> + drive-strength= <2>; >> + bias-disable; >> + }; > You can bunch these two up like this: > > qupv3_se1_2uart_active: qup.... { > tx { > pins = ... > foo = ... > }; > > rx { > pins = ... > bar = ... > }; > }; Sure will do this in the next version having all this in the single patch. Thanks, Rohit. > Konrad >> + >> + qupv3_se1_2uart_rx_active: qupv3-se1-2uart-rx-active-state { >> + pins = "gpio13"; >> + function = "qup_se1_l3_mira"; >> + drive-strength= <2>; >> + bias-disable; >> + }; >> + >> + qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { >> + pins = "gpio12", "gpio13"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-down; >> + }; >> }; >> >> apps_smmu: iommu@15000000 {
diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index f83eef8..47170ae 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -385,6 +385,34 @@ #power-domain-cells = <1>; }; + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart1: serial@984000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00984000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qupv3_se1_2uart_tx_active>, + <&qupv3_se1_2uart_rx_active>; + pinctrl-1 = <&qupv3_se1_2uart_sleep>; + pinctrl-names = "default", + "sleep"; + status = "disabled"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -413,6 +441,27 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; + + qupv3_se1_2uart_tx_active: qupv3-se1-2uart-tx-active-state { + pins = "gpio12"; + function = "qup_se1_l2_mira"; + drive-strength= <2>; + bias-disable; + }; + + qupv3_se1_2uart_rx_active: qupv3-se1-2uart-rx-active-state { + pins = "gpio13"; + function = "qup_se1_l3_mira"; + drive-strength= <2>; + bias-disable; + }; + + qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; }; apps_smmu: iommu@15000000 {
Add the debug uart console node in devicetree. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+)