| Message ID | 20230523135351.19133-6-ddrokosov@sberdevices.ru (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add Amlogic A1 clock controller drivers | expand |
Hello Rob, Krzysztof and Conor, Could you please take a look at this patch version? Before Rob marked this patchset with RvB at v13 - https://lore.kernel.org/linux-amlogic/168130720431.2218249.7671061964988064525.robh@kernel.org/ However, due to several comments from other maintainers, unfortunately, I had to rename the 'a1-clkc' controller to 'a1-peripherals-clkc' and remove Rob's RvB. I would be grateful for your assistance! On Tue, May 23, 2023 at 04:53:50PM +0300, Dmitry Rokosov wrote: > Add documentation and dt bindings for the Amlogic A1 Peripherals clock > controller. > A1 PLL clock controller has references to A1 Peripherals clock > controller objects, so reflect them in the schema. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> > --- > .../clock/amlogic,a1-peripherals-clkc.yaml | 73 +++++++++++ > .../bindings/clock/amlogic,a1-pll-clkc.yaml | 5 +- > .../clock/amlogic,a1-peripherals-clkc.h | 115 ++++++++++++++++++ > 3 files changed, 191 insertions(+), 2 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > create mode 100644 include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > new file mode 100644 > index 000000000000..6d84cee1bd75 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > @@ -0,0 +1,73 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Amlogic A1 Peripherals Clock Control Unit > + > +maintainers: > + - Neil Armstrong <neil.armstrong@linaro.org> > + - Jerome Brunet <jbrunet@baylibre.com> > + - Jian Hu <jian.hu@jian.hu.com> > + - Dmitry Rokosov <ddrokosov@sberdevices.ru> > + > +properties: > + compatible: > + const: amlogic,a1-peripherals-clkc > + > + '#clock-cells': > + const: 1 > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: input fixed pll div2 > + - description: input fixed pll div3 > + - description: input fixed pll div5 > + - description: input fixed pll div7 > + - description: input hifi pll > + - description: input oscillator (usually at 24MHz) > + > + clock-names: > + items: > + - const: fclk_div2 > + - const: fclk_div3 > + - const: fclk_div5 > + - const: fclk_div7 > + - const: hifi_pll > + - const: xtal > + > +required: > + - compatible > + - '#clock-cells' > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/amlogic,a1-pll-clkc.h> > + apb { > + #address-cells = <2>; > + #size-cells = <2>; > + > + clock-controller@800 { > + compatible = "amlogic,a1-peripherals-clkc"; > + reg = <0 0x800 0 0x104>; > + #clock-cells = <1>; > + clocks = <&clkc_pll CLKID_FCLK_DIV2>, > + <&clkc_pll CLKID_FCLK_DIV3>, > + <&clkc_pll CLKID_FCLK_DIV5>, > + <&clkc_pll CLKID_FCLK_DIV7>, > + <&clkc_pll CLKID_HIFI_PLL>, > + <&xtal>; > + clock-names = "fclk_div2", "fclk_div3", > + "fclk_div5", "fclk_div7", > + "hifi_pll", "xtal"; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > index 5c6fa620a63c..a59b188a8bf5 100644 > --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > @@ -43,6 +43,7 @@ additionalProperties: false > > examples: > - | > + #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> > apb { > #address-cells = <2>; > #size-cells = <2>; > @@ -51,8 +52,8 @@ examples: > compatible = "amlogic,a1-pll-clkc"; > reg = <0 0x7c80 0 0x18c>; > #clock-cells = <1>; > - clocks = <&clkc_periphs_fixpll_in>, > - <&clkc_periphs_hifipll_in>; > + clocks = <&clkc_periphs CLKID_FIXPLL_IN>, > + <&clkc_periphs CLKID_HIFIPLL_IN>; > clock-names = "fixpll_in", "hifipll_in"; > }; > }; > diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h > new file mode 100644 > index 000000000000..ff2730f398a6 > --- /dev/null > +++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h > @@ -0,0 +1,115 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > +/* > + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. > + * Author: Jian Hu <jian.hu@amlogic.com> > + * > + * Copyright (c) 2023, SberDevices. All Rights Reserved. > + * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> > + */ > + > +#ifndef __A1_PERIPHERALS_CLKC_H > +#define __A1_PERIPHERALS_CLKC_H > + > +#define CLKID_FIXPLL_IN 1 > +#define CLKID_USB_PHY_IN 2 > +#define CLKID_USB_CTRL_IN 3 > +#define CLKID_HIFIPLL_IN 4 > +#define CLKID_SYSPLL_IN 5 > +#define CLKID_DDS_IN 6 > +#define CLKID_SYS 7 > +#define CLKID_CLKTREE 8 > +#define CLKID_RESET_CTRL 9 > +#define CLKID_ANALOG_CTRL 10 > +#define CLKID_PWR_CTRL 11 > +#define CLKID_PAD_CTRL 12 > +#define CLKID_SYS_CTRL 13 > +#define CLKID_TEMP_SENSOR 14 > +#define CLKID_AM2AXI_DIV 15 > +#define CLKID_SPICC_B 16 > +#define CLKID_SPICC_A 17 > +#define CLKID_MSR 18 > +#define CLKID_AUDIO 19 > +#define CLKID_JTAG_CTRL 20 > +#define CLKID_SARADC_EN 21 > +#define CLKID_PWM_EF 22 > +#define CLKID_PWM_CD 23 > +#define CLKID_PWM_AB 24 > +#define CLKID_CEC 25 > +#define CLKID_I2C_S 26 > +#define CLKID_IR_CTRL 27 > +#define CLKID_I2C_M_D 28 > +#define CLKID_I2C_M_C 29 > +#define CLKID_I2C_M_B 30 > +#define CLKID_I2C_M_A 31 > +#define CLKID_ACODEC 32 > +#define CLKID_OTP 33 > +#define CLKID_SD_EMMC_A 34 > +#define CLKID_USB_PHY 35 > +#define CLKID_USB_CTRL 36 > +#define CLKID_SYS_DSPB 37 > +#define CLKID_SYS_DSPA 38 > +#define CLKID_DMA 39 > +#define CLKID_IRQ_CTRL 40 > +#define CLKID_NIC 41 > +#define CLKID_GIC 42 > +#define CLKID_UART_C 43 > +#define CLKID_UART_B 44 > +#define CLKID_UART_A 45 > +#define CLKID_SYS_PSRAM 46 > +#define CLKID_RSA 47 > +#define CLKID_CORESIGHT 48 > +#define CLKID_AM2AXI_VAD 49 > +#define CLKID_AUDIO_VAD 50 > +#define CLKID_AXI_DMC 51 > +#define CLKID_AXI_PSRAM 52 > +#define CLKID_RAMB 53 > +#define CLKID_RAMA 54 > +#define CLKID_AXI_SPIFC 55 > +#define CLKID_AXI_NIC 56 > +#define CLKID_AXI_DMA 57 > +#define CLKID_CPU_CTRL 58 > +#define CLKID_ROM 59 > +#define CLKID_PROC_I2C 60 > +#define CLKID_DSPA_EN 63 > +#define CLKID_DSPA_EN_NIC 64 > +#define CLKID_DSPB_EN 65 > +#define CLKID_DSPB_EN_NIC 66 > +#define CLKID_RTC 67 > +#define CLKID_CECA_32K 68 > +#define CLKID_CECB_32K 69 > +#define CLKID_24M 70 > +#define CLKID_12M 71 > +#define CLKID_FCLK_DIV2_DIVN 72 > +#define CLKID_GEN 73 > +#define CLKID_SARADC 75 > +#define CLKID_PWM_A 76 > +#define CLKID_PWM_B 77 > +#define CLKID_PWM_C 78 > +#define CLKID_PWM_D 79 > +#define CLKID_PWM_E 80 > +#define CLKID_PWM_F 81 > +#define CLKID_SPICC 82 > +#define CLKID_TS 83 > +#define CLKID_SPIFC 84 > +#define CLKID_USB_BUS 85 > +#define CLKID_SD_EMMC 86 > +#define CLKID_PSRAM 87 > +#define CLKID_DMC 88 > +#define CLKID_DSPA_A_SEL 95 > +#define CLKID_DSPA_B_SEL 98 > +#define CLKID_DSPB_A_SEL 101 > +#define CLKID_DSPB_B_SEL 104 > +#define CLKID_CECB_32K_SEL_PRE 113 > +#define CLKID_CECB_32K_SEL 114 > +#define CLKID_CECA_32K_SEL_PRE 117 > +#define CLKID_CECA_32K_SEL 118 > +#define CLKID_GEN_SEL 121 > +#define CLKID_PWM_A_SEL 124 > +#define CLKID_PWM_B_SEL 126 > +#define CLKID_PWM_C_SEL 128 > +#define CLKID_PWM_D_SEL 130 > +#define CLKID_PWM_E_SEL 132 > +#define CLKID_PWM_F_SEL 134 > +#define CLKID_SD_EMMC_SEL2 147 > + > +#endif /* __A1_PERIPHERALS_CLKC_H */ > -- > 2.36.0 >
On Thu, May 25, 2023 at 12:37:36PM +0300, Dmitry Rokosov wrote: > Hello Rob, Krzysztof and Conor, > > Could you please take a look at this patch version? Before Rob marked > this patchset with RvB at v13 - > https://lore.kernel.org/linux-amlogic/168130720431.2218249.7671061964988064525.robh@kernel.org/ > > However, due to several comments from other maintainers, unfortunately, > I had to rename the 'a1-clkc' controller to 'a1-peripherals-clkc' and > remove Rob's RvB. I dunno if the compatible change is worth dropping the tag for tbh. That seems to be the only change, so I guess you can have my R-b instead of Rob's... Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
Conor, Thank you for quick reply! On Thu, May 25, 2023 at 02:16:02PM +0100, Conor Dooley wrote: > On Thu, May 25, 2023 at 12:37:36PM +0300, Dmitry Rokosov wrote: > > Hello Rob, Krzysztof and Conor, > > > > Could you please take a look at this patch version? Before Rob marked > > this patchset with RvB at v13 - > > https://lore.kernel.org/linux-amlogic/168130720431.2218249.7671061964988064525.robh@kernel.org/ > > > > However, due to several comments from other maintainers, unfortunately, > > I had to rename the 'a1-clkc' controller to 'a1-peripherals-clkc' and > > remove Rob's RvB. > > I dunno if the compatible change is worth dropping the tag for tbh. > That seems to be the only change, so I guess you can have my R-b instead > of Rob's... > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Cheers, > Conor. I was unaware of the official policy regarding the removal of RvB during renaming changes. I took a cautious approach to the situation :)
On Thu, May 25, 2023 at 05:01:00PM +0300, Dmitry Rokosov wrote: > I was unaware of the official policy regarding the removal of RvB during > renaming changes. I took a cautious approach to the situation :) Better safe than sorry!
On Tue, 23 May 2023 16:53:50 +0300, Dmitry Rokosov wrote: > Add documentation and dt bindings for the Amlogic A1 Peripherals clock > controller. > A1 PLL clock controller has references to A1 Peripherals clock > controller objects, so reflect them in the schema. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> > --- > .../clock/amlogic,a1-peripherals-clkc.yaml | 73 +++++++++++ > .../bindings/clock/amlogic,a1-pll-clkc.yaml | 5 +- > .../clock/amlogic,a1-peripherals-clkc.h | 115 ++++++++++++++++++ > 3 files changed, 191 insertions(+), 2 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > create mode 100644 include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml new file mode 100644 index 000000000000..6d84cee1bd75 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A1 Peripherals Clock Control Unit + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Jerome Brunet <jbrunet@baylibre.com> + - Jian Hu <jian.hu@jian.hu.com> + - Dmitry Rokosov <ddrokosov@sberdevices.ru> + +properties: + compatible: + const: amlogic,a1-peripherals-clkc + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: input fixed pll div2 + - description: input fixed pll div3 + - description: input fixed pll div5 + - description: input fixed pll div7 + - description: input hifi pll + - description: input oscillator (usually at 24MHz) + + clock-names: + items: + - const: fclk_div2 + - const: fclk_div3 + - const: fclk_div5 + - const: fclk_div7 + - const: hifi_pll + - const: xtal + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/amlogic,a1-pll-clkc.h> + apb { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@800 { + compatible = "amlogic,a1-peripherals-clkc"; + reg = <0 0x800 0 0x104>; + #clock-cells = <1>; + clocks = <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV5>, + <&clkc_pll CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_HIFI_PLL>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div3", + "fclk_div5", "fclk_div7", + "hifi_pll", "xtal"; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml index 5c6fa620a63c..a59b188a8bf5 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml @@ -43,6 +43,7 @@ additionalProperties: false examples: - | + #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> apb { #address-cells = <2>; #size-cells = <2>; @@ -51,8 +52,8 @@ examples: compatible = "amlogic,a1-pll-clkc"; reg = <0 0x7c80 0 0x18c>; #clock-cells = <1>; - clocks = <&clkc_periphs_fixpll_in>, - <&clkc_periphs_hifipll_in>; + clocks = <&clkc_periphs CLKID_FIXPLL_IN>, + <&clkc_periphs CLKID_HIFIPLL_IN>; clock-names = "fixpll_in", "hifipll_in"; }; }; diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h new file mode 100644 index 000000000000..ff2730f398a6 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu <jian.hu@amlogic.com> + * + * Copyright (c) 2023, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> + */ + +#ifndef __A1_PERIPHERALS_CLKC_H +#define __A1_PERIPHERALS_CLKC_H + +#define CLKID_FIXPLL_IN 1 +#define CLKID_USB_PHY_IN 2 +#define CLKID_USB_CTRL_IN 3 +#define CLKID_HIFIPLL_IN 4 +#define CLKID_SYSPLL_IN 5 +#define CLKID_DDS_IN 6 +#define CLKID_SYS 7 +#define CLKID_CLKTREE 8 +#define CLKID_RESET_CTRL 9 +#define CLKID_ANALOG_CTRL 10 +#define CLKID_PWR_CTRL 11 +#define CLKID_PAD_CTRL 12 +#define CLKID_SYS_CTRL 13 +#define CLKID_TEMP_SENSOR 14 +#define CLKID_AM2AXI_DIV 15 +#define CLKID_SPICC_B 16 +#define CLKID_SPICC_A 17 +#define CLKID_MSR 18 +#define CLKID_AUDIO 19 +#define CLKID_JTAG_CTRL 20 +#define CLKID_SARADC_EN 21 +#define CLKID_PWM_EF 22 +#define CLKID_PWM_CD 23 +#define CLKID_PWM_AB 24 +#define CLKID_CEC 25 +#define CLKID_I2C_S 26 +#define CLKID_IR_CTRL 27 +#define CLKID_I2C_M_D 28 +#define CLKID_I2C_M_C 29 +#define CLKID_I2C_M_B 30 +#define CLKID_I2C_M_A 31 +#define CLKID_ACODEC 32 +#define CLKID_OTP 33 +#define CLKID_SD_EMMC_A 34 +#define CLKID_USB_PHY 35 +#define CLKID_USB_CTRL 36 +#define CLKID_SYS_DSPB 37 +#define CLKID_SYS_DSPA 38 +#define CLKID_DMA 39 +#define CLKID_IRQ_CTRL 40 +#define CLKID_NIC 41 +#define CLKID_GIC 42 +#define CLKID_UART_C 43 +#define CLKID_UART_B 44 +#define CLKID_UART_A 45 +#define CLKID_SYS_PSRAM 46 +#define CLKID_RSA 47 +#define CLKID_CORESIGHT 48 +#define CLKID_AM2AXI_VAD 49 +#define CLKID_AUDIO_VAD 50 +#define CLKID_AXI_DMC 51 +#define CLKID_AXI_PSRAM 52 +#define CLKID_RAMB 53 +#define CLKID_RAMA 54 +#define CLKID_AXI_SPIFC 55 +#define CLKID_AXI_NIC 56 +#define CLKID_AXI_DMA 57 +#define CLKID_CPU_CTRL 58 +#define CLKID_ROM 59 +#define CLKID_PROC_I2C 60 +#define CLKID_DSPA_EN 63 +#define CLKID_DSPA_EN_NIC 64 +#define CLKID_DSPB_EN 65 +#define CLKID_DSPB_EN_NIC 66 +#define CLKID_RTC 67 +#define CLKID_CECA_32K 68 +#define CLKID_CECB_32K 69 +#define CLKID_24M 70 +#define CLKID_12M 71 +#define CLKID_FCLK_DIV2_DIVN 72 +#define CLKID_GEN 73 +#define CLKID_SARADC 75 +#define CLKID_PWM_A 76 +#define CLKID_PWM_B 77 +#define CLKID_PWM_C 78 +#define CLKID_PWM_D 79 +#define CLKID_PWM_E 80 +#define CLKID_PWM_F 81 +#define CLKID_SPICC 82 +#define CLKID_TS 83 +#define CLKID_SPIFC 84 +#define CLKID_USB_BUS 85 +#define CLKID_SD_EMMC 86 +#define CLKID_PSRAM 87 +#define CLKID_DMC 88 +#define CLKID_DSPA_A_SEL 95 +#define CLKID_DSPA_B_SEL 98 +#define CLKID_DSPB_A_SEL 101 +#define CLKID_DSPB_B_SEL 104 +#define CLKID_CECB_32K_SEL_PRE 113 +#define CLKID_CECB_32K_SEL 114 +#define CLKID_CECA_32K_SEL_PRE 117 +#define CLKID_CECA_32K_SEL 118 +#define CLKID_GEN_SEL 121 +#define CLKID_PWM_A_SEL 124 +#define CLKID_PWM_B_SEL 126 +#define CLKID_PWM_C_SEL 128 +#define CLKID_PWM_D_SEL 130 +#define CLKID_PWM_E_SEL 132 +#define CLKID_PWM_F_SEL 134 +#define CLKID_SD_EMMC_SEL2 147 + +#endif /* __A1_PERIPHERALS_CLKC_H */