diff mbox series

[v2,2/3] ufs: poll HCS.UCRDY before issuing a UIC command

Message ID 40006660eaece22f76b9532c70479d719655b33f.1685927620.git.kwmad.kim@samsung.com (mailing list archive)
State Superseded
Headers show
Series change UIC command handling | expand

Commit Message

Kiwoong Kim June 5, 2023, 1:15 a.m. UTC
v1 -> v2: replace usleep_range with udelay
because it's a sleepable period.

With auto hibern8 enabled, UIC could be working
for a while to process a hibern8 operation and HCI
reports UIC not ready for a short term through HCS.UCRDY.
And UFS driver can't recognize the operation.
UFSHCI spec specifies UCRDY like this:
whether the host controller is ready to process UIC COMMAND

The 'ready' could be seen as many different meanings. If the meaning
includes not processing any request from HCI, processing a hibern8
operation can be 'not ready'. In this situation, the driver needs to
wait until the operations is completed.

Signed-off-by: Kiwoong Kim <kwmad.kim@samsung.com>
---
 drivers/ufs/core/ufshcd.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Comments

Avri Altman June 5, 2023, 7:05 a.m. UTC | #1
> v1 -> v2: replace usleep_range with udelay because it's a sleepable period.
> 
> With auto hibern8 enabled, UIC could be working for a while to process a
> hibern8 operation and HCI reports UIC not ready for a short term through
> HCS.UCRDY.
> And UFS driver can't recognize the operation.
> UFSHCI spec specifies UCRDY like this:
> whether the host controller is ready to process UIC COMMAND
> 
> The 'ready' could be seen as many different meanings. If the meaning includes
> not processing any request from HCI, processing a hibern8 operation can be
> 'not ready'. In this situation, the driver needs to wait until the operations is
> completed.
> 
> Signed-off-by: Kiwoong Kim <kwmad.kim@samsung.com>
> ---
>  drivers/ufs/core/ufshcd.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index
> a89d39a..1f58a20 100644
> --- a/drivers/ufs/core/ufshcd.c
> +++ b/drivers/ufs/core/ufshcd.c
> @@ -2365,7 +2365,18 @@ static inline int ufshcd_hba_capabilities(struct
> ufs_hba *hba)
>   */
>  static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)  {
> -       return ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
> UIC_COMMAND_READY;
> +       ktime_t timeout = ktime_add_ms(ktime_get(), UIC_CMD_TIMEOUT);
> +       u32 val = 0;
> +
> +       do {
> +               val = ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
> +                       UIC_COMMAND_READY;
> +               if (val)
> +                       break;
> +               udelay(500);
> +       } while (ktime_before(ktime_get(), timeout));
> +
> +       return val ? true : false;
>  }
Can you use read_poll_timeout() instead?

Thanks,
Avri

> 
>  /**
> --
> 2.7.4
Kiwoong Kim June 8, 2023, 2:38 a.m. UTC | #2
> >  static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)  {
> > -       return ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
> > UIC_COMMAND_READY;
> > +       ktime_t timeout = ktime_add_ms(ktime_get(), UIC_CMD_TIMEOUT);
> > +       u32 val = 0;
> > +
> > +       do {
> > +               val = ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
> > +                       UIC_COMMAND_READY;
> > +               if (val)
> > +                       break;
> > +               udelay(500);
> > +       } while (ktime_before(ktime_get(), timeout));
> > +
> > +       return val ? true : false;
> >  }
> Can you use read_poll_timeout() instead?
> 
> Thanks,
> Avri

Okay, thanks.
diff mbox series

Patch

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index a89d39a..1f58a20 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -2365,7 +2365,18 @@  static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
  */
 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
 {
-	return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY;
+	ktime_t timeout = ktime_add_ms(ktime_get(), UIC_CMD_TIMEOUT);
+	u32 val = 0;
+
+	do {
+		val = ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
+			UIC_COMMAND_READY;
+		if (val)
+			break;
+		udelay(500);
+	} while (ktime_before(ktime_get(), timeout));
+
+	return val ? true : false;
 }
 
 /**