| Message ID | 20230615050015.3105902-7-dnyaneshwar.bhadane@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Replace acronym with full platform name in defines. | expand |
Apart from the platform subject prefix, Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > -----Original Message----- > From: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com> > Sent: Wednesday, June 14, 2023 10:00 PM > To: intel-gfx@lists.freedesktop.org > Cc: Atwood, Matthew S <matthew.s.atwood@intel.com>; Srivatsa, Anusha > <anusha.srivatsa@intel.com>; Bhadane, Dnyaneshwar > <dnyaneshwar.bhadane@intel.com> > Subject: [PATCH 06/11] drm/i915/SKL: s/SKL/SKYLAKE for platform/subplatform > defines > > Follow consistent naming convention. Replace SKL with SKYLAKE. > > Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++-- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 14 +++++++------- > 3 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index 84b09d188d2a..ab84d003232c 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1724,9 +1724,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder > *encoder) > encoder->get_buf_trans = kbl_u_get_buf_trans; > } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || > IS_KABYLAKE(i915)) { > encoder->get_buf_trans = kbl_get_buf_trans; > - } else if (IS_SKL_ULX(i915)) { > + } else if (IS_SKYLAKE_ULX(i915)) { > encoder->get_buf_trans = skl_y_get_buf_trans; > - } else if (IS_SKL_ULT(i915)) { > + } else if (IS_SKYLAKE_ULT(i915)) { > encoder->get_buf_trans = skl_u_get_buf_trans; > } else if (IS_SKYLAKE(i915)) { > encoder->get_buf_trans = skl_get_buf_trans; diff --git > a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index b632fb5592a8..10a4e0fc23ec 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1173,7 +1173,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct > i915_wa_list *wal) > GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); > > /* WaInPlaceDecompressionHang:skl */ > - if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) > + if (IS_SKYLAKE_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) > wa_write_or(wal, > GEN9_GAMT_ECO_REG_RW_IA, > GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index f19915115cff..3c4a66f1a7ba 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -610,19 +610,19 @@ IS_SUBPLATFORM(const struct drm_i915_private > *i915, > /* ULX machines are also considered ULT. */ #define IS_HSW_ULX(i915) \ > IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) - > #define IS_SKL_ULT(i915) \ > +#define IS_SKYLAKE_ULT(i915) \ > IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) - > #define IS_SKL_ULX(i915) \ > +#define IS_SKYLAKE_ULX(i915) \ > IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) > #define IS_KABYLAKE_ULT(i915) \ > IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) > #define IS_KABYLAKE_ULX(i915) \ > IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) > -#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \ > +#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \ > INTEL_INFO(i915)->gt == 2) > -#define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \ > +#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \ > INTEL_INFO(i915)->gt == 3) > -#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \ > +#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \ > INTEL_INFO(i915)->gt == 4) > #define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \ > INTEL_INFO(i915)->gt == 2) > @@ -650,7 +650,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_TIGERLAKE_UY(i915) \ > IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) > > -#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && > IS_GRAPHICS_STEP(p, since, until)) > +#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && > +IS_GRAPHICS_STEP(p, since, until)) > > #define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \ > (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until)) @@ - > 801,7 +801,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > /* WaRsDisableCoarsePowerGating:skl,cnl */ > #define NEEDS_WaRsDisableCoarsePowerGating(i915) \ > - (IS_SKL_GT3(i915) || IS_SKL_GT4(i915)) > + (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915)) > > /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte > * rows, which changed the alignment requirements and fence programming. > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 84b09d188d2a..ab84d003232c 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1724,9 +1724,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) encoder->get_buf_trans = kbl_u_get_buf_trans; } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) { encoder->get_buf_trans = kbl_get_buf_trans; - } else if (IS_SKL_ULX(i915)) { + } else if (IS_SKYLAKE_ULX(i915)) { encoder->get_buf_trans = skl_y_get_buf_trans; - } else if (IS_SKL_ULT(i915)) { + } else if (IS_SKYLAKE_ULT(i915)) { encoder->get_buf_trans = skl_u_get_buf_trans; } else if (IS_SKYLAKE(i915)) { encoder->get_buf_trans = skl_get_buf_trans; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index b632fb5592a8..10a4e0fc23ec 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1173,7 +1173,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); /* WaInPlaceDecompressionHang:skl */ - if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) + if (IS_SKYLAKE_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) wa_write_or(wal, GEN9_GAMT_ECO_REG_RW_IA, GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f19915115cff..3c4a66f1a7ba 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -610,19 +610,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, /* ULX machines are also considered ULT. */ #define IS_HSW_ULX(i915) \ IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) -#define IS_SKL_ULT(i915) \ +#define IS_SKYLAKE_ULT(i915) \ IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) -#define IS_SKL_ULX(i915) \ +#define IS_SKYLAKE_ULX(i915) \ IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) #define IS_KABYLAKE_ULT(i915) \ IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) #define IS_KABYLAKE_ULX(i915) \ IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) -#define IS_SKL_GT2(i915) (IS_SKYLAKE(i915) && \ +#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \ INTEL_INFO(i915)->gt == 2) -#define IS_SKL_GT3(i915) (IS_SKYLAKE(i915) && \ +#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \ INTEL_INFO(i915)->gt == 3) -#define IS_SKL_GT4(i915) (IS_SKYLAKE(i915) && \ +#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \ INTEL_INFO(i915)->gt == 4) #define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \ INTEL_INFO(i915)->gt == 2) @@ -650,7 +650,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_TIGERLAKE_UY(i915) \ IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) -#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) +#define IS_SKYLAKE_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) #define IS_KABYLAKE_GRAPHICS_STEP(i915, since, until) \ (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until)) @@ -801,7 +801,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, /* WaRsDisableCoarsePowerGating:skl,cnl */ #define NEEDS_WaRsDisableCoarsePowerGating(i915) \ - (IS_SKL_GT3(i915) || IS_SKL_GT4(i915)) + (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915)) /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming.
Follow consistent naming convention. Replace SKL with SKYLAKE. Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 14 +++++++------- 3 files changed, 10 insertions(+), 10 deletions(-)