| Message ID | 20230614104759.228372-4-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add non-coherent DMA support for AX45MP | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes, riscv/for-next or riscv/master |
On Wed, Jun 14, 2023, at 12:47, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Introduce support for nonstandard noncoherent systems in the RISC-V > architecture. It enables function pointer support to handle cache > management in such systems. > > This patch adds a new configuration option called > "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that > depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer > support for cache management in nonstandard noncoherent systems. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> I understand that Christoph will still not like this, but I think this is as good as it gets, making the standard variant the fast path, and using the function pointers only for the nonstandard cases. > #include <asm/cacheflush.h> > +#include <asm/dma-noncoherent.h> > > static bool noncoherent_supported; > > +struct riscv_cache_ops noncoherent_cache_ops = { > + .clean = NULL, > + .inval = NULL, > + .flush = NULL, > +}; This could be marked __read_mostly or __ro_after_init as a micro-optimization, if anyone cares. Arnd
Hi Prabhakar, On Wed, Jun 14, 2023 at 12:48 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Introduce support for nonstandard noncoherent systems in the RISC-V > architecture. It enables function pointer support to handle cache > management in such systems. > > This patch adds a new configuration option called > "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that > depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer > support for cache management in nonstandard noncoherent systems. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v8 -> v9 > * New patch Thanks for your patch! > --- /dev/null > +++ b/arch/riscv/include/asm/dma-noncoherent.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2023 Renesas Electronics Corp. > + */ > + > +#ifndef __ASM_DMA_NONCOHERENT_H > +#define __ASM_DMA_NONCOHERENT_H > + > +#include <linux/dma-direct.h> > + > +/* > + * struct riscv_cache_ops - Structure for CMO function pointers > + * > + * @clean: Function pointer for clean cache > + * @inval: Function pointer for invalidate cache > + * @flush: Function pointer for flushing the cache > + */ > +struct riscv_cache_ops { > + void (*clean)(phys_addr_t paddr, unsigned long size); > + void (*inval)(phys_addr_t paddr, unsigned long size); > + void (*flush)(phys_addr_t paddr, unsigned long size); > +}; I guess the naming can be improved? .clean() is used by arch_dma_cache_wback() / arch_wb_cache_pmem(), .inval() is used by arch_dma_cache_inv() / arch_invalidate_pmem(), .flush() is used by arch_dma_cache_wback_inv() / arch_dma_prep_coherent(). Perhaps .wback(), .inv(), .wback_inv() are more clear? I understand this is subject to bikeshedding... But hey, how many innocent bits of data have already been lost due to cache semantic mismatches? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Wed, Jun 14, 2023 at 02:53:26PM +0200, Geert Uytterhoeven wrote: > Hi Prabhakar, > > On Wed, Jun 14, 2023 at 12:48 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Introduce support for nonstandard noncoherent systems in the RISC-V > > architecture. It enables function pointer support to handle cache > > management in such systems. > > > > This patch adds a new configuration option called > > "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that > > depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer > > support for cache management in nonstandard noncoherent systems. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v8 -> v9 > > * New patch > > Thanks for your patch! > > > --- /dev/null > > +++ b/arch/riscv/include/asm/dma-noncoherent.h > > @@ -0,0 +1,28 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (C) 2023 Renesas Electronics Corp. > > + */ > > + > > +#ifndef __ASM_DMA_NONCOHERENT_H > > +#define __ASM_DMA_NONCOHERENT_H > > + > > +#include <linux/dma-direct.h> > > + > > +/* > > + * struct riscv_cache_ops - Structure for CMO function pointers > > + * > > + * @clean: Function pointer for clean cache > > + * @inval: Function pointer for invalidate cache > > + * @flush: Function pointer for flushing the cache > > + */ > > +struct riscv_cache_ops { > > + void (*clean)(phys_addr_t paddr, unsigned long size); > > + void (*inval)(phys_addr_t paddr, unsigned long size); > > + void (*flush)(phys_addr_t paddr, unsigned long size); > > +}; > > I guess the naming can be improved? > > .clean() is used by arch_dma_cache_wback() / arch_wb_cache_pmem(), > .inval() is used by arch_dma_cache_inv() / arch_invalidate_pmem(), > .flush() is used by arch_dma_cache_wback_inv() / arch_dma_prep_coherent(). > > Perhaps .wback(), .inv(), .wback_inv() are more clear? > > I understand this is subject to bikeshedding... > But hey, how many innocent bits of data have already been lost due > to cache semantic mismatches? Given this is based on Arnd's stuff, +1 on the bikeshed. The names have been chosen I guess to match the CBOM extensions naming. Otherwise, I had it in my head that the next revision of this was going to take patches 8 & 9 from Arnd's series, to align the semantics. Not that it really bothers me, just means this will have to wait for the cross-arch series, when pretty sure Arnd suggested not depending on that any more... Am I missing something Prabhakar? Other than the bikeshedding, no objections. Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
On Wed, Jun 14, 2023 at 02:35:44PM +0200, Arnd Bergmann wrote: > I understand that Christoph will still not like this, but I think this > is as good as it gets, making the standard variant the fast path, > and using the function pointers only for the nonstandard cases. Yes. And I really do not want to make the non-standard cases easy. The extension to do cache maintenance have been ratified for a while and under discussion for much longer. Adding random crap because vendors suck is a bad idea, and we should not be adding this crap.
Hi Arnd, Thank you for the review. On Wed, Jun 14, 2023 at 1:36 PM Arnd Bergmann <arnd@arndb.de> wrote: > > On Wed, Jun 14, 2023, at 12:47, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Introduce support for nonstandard noncoherent systems in the RISC-V > > architecture. It enables function pointer support to handle cache > > management in such systems. > > > > This patch adds a new configuration option called > > "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that > > depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer > > support for cache management in nonstandard noncoherent systems. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > I understand that Christoph will still not like this, but I think this > is as good as it gets, making the standard variant the fast path, > and using the function pointers only for the nonstandard cases. > > > > #include <asm/cacheflush.h> > > +#include <asm/dma-noncoherent.h> > > > > static bool noncoherent_supported; > > > > +struct riscv_cache_ops noncoherent_cache_ops = { > > + .clean = NULL, > > + .inval = NULL, > > + .flush = NULL, > > +}; > > This could be marked __read_mostly or __ro_after_init as > a micro-optimization, if anyone cares. > Ok, I will do that in the next version. Cheers, Prabhakar
Hi Geert, Thank you for the review. On Wed, Jun 14, 2023 at 1:53 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Wed, Jun 14, 2023 at 12:48 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Introduce support for nonstandard noncoherent systems in the RISC-V > > architecture. It enables function pointer support to handle cache > > management in such systems. > > > > This patch adds a new configuration option called > > "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that > > depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer > > support for cache management in nonstandard noncoherent systems. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v8 -> v9 > > * New patch > > Thanks for your patch! > > > --- /dev/null > > +++ b/arch/riscv/include/asm/dma-noncoherent.h > > @@ -0,0 +1,28 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (C) 2023 Renesas Electronics Corp. > > + */ > > + > > +#ifndef __ASM_DMA_NONCOHERENT_H > > +#define __ASM_DMA_NONCOHERENT_H > > + > > +#include <linux/dma-direct.h> > > + > > +/* > > + * struct riscv_cache_ops - Structure for CMO function pointers > > + * > > + * @clean: Function pointer for clean cache > > + * @inval: Function pointer for invalidate cache > > + * @flush: Function pointer for flushing the cache > > + */ > > +struct riscv_cache_ops { > > + void (*clean)(phys_addr_t paddr, unsigned long size); > > + void (*inval)(phys_addr_t paddr, unsigned long size); > > + void (*flush)(phys_addr_t paddr, unsigned long size); > > +}; > > I guess the naming can be improved? > > .clean() is used by arch_dma_cache_wback() / arch_wb_cache_pmem(), > .inval() is used by arch_dma_cache_inv() / arch_invalidate_pmem(), > .flush() is used by arch_dma_cache_wback_inv() / arch_dma_prep_coherent(). > > Perhaps .wback(), .inv(), .wback_inv() are more clear? > Ok I will update pointer names in the next version. Cheers, Prabhakar
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 628aad4fb6e2..325ab2124f0a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -261,6 +261,13 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SYNC_DMA_FOR_DEVICE select DMA_DIRECT_REMAP +config RISCV_NONSTANDARD_CACHE_OPS + bool + depends on RISCV_DMA_NONCOHERENT + help + This enables function pointer support for non-standard noncoherent + systems to handle cache management. + config AS_HAS_INSN def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) diff --git a/arch/riscv/include/asm/dma-noncoherent.h b/arch/riscv/include/asm/dma-noncoherent.h new file mode 100644 index 000000000000..f4e9bb2d3800 --- /dev/null +++ b/arch/riscv/include/asm/dma-noncoherent.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#ifndef __ASM_DMA_NONCOHERENT_H +#define __ASM_DMA_NONCOHERENT_H + +#include <linux/dma-direct.h> + +/* + * struct riscv_cache_ops - Structure for CMO function pointers + * + * @clean: Function pointer for clean cache + * @inval: Function pointer for invalidate cache + * @flush: Function pointer for flushing the cache + */ +struct riscv_cache_ops { + void (*clean)(phys_addr_t paddr, unsigned long size); + void (*inval)(phys_addr_t paddr, unsigned long size); + void (*flush)(phys_addr_t paddr, unsigned long size); +}; + +extern struct riscv_cache_ops noncoherent_cache_ops; + +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops); + +#endif /* __ASM_DMA_NONCOHERENT_H */ diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b9a9f57e02be..4cdaa879839a 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -9,13 +9,26 @@ #include <linux/dma-map-ops.h> #include <linux/mm.h> #include <asm/cacheflush.h> +#include <asm/dma-noncoherent.h> static bool noncoherent_supported; +struct riscv_cache_ops noncoherent_cache_ops = { + .clean = NULL, + .inval = NULL, + .flush = NULL, +}; + static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.clean)) { + noncoherent_cache_ops.clean(paddr, size); + return; + } +#endif ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); } @@ -23,6 +36,13 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.inval)) { + noncoherent_cache_ops.inval(paddr, size); + return; + } +#endif + ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); } @@ -30,6 +50,13 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.flush)) { + noncoherent_cache_ops.flush(paddr, size); + return; + } +#endif + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); } @@ -50,6 +77,13 @@ void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.flush)) { + noncoherent_cache_ops.flush(page_to_phys(page), size); + return; + } +#endif + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); } @@ -75,3 +109,12 @@ void riscv_noncoherent_supported(void) "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; } + +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops) +{ + if (!ops) + return; + + noncoherent_cache_ops = *ops; +} +EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops); diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c index 089df92ae876..fb481f5b930a 100644 --- a/arch/riscv/mm/pmem.c +++ b/arch/riscv/mm/pmem.c @@ -7,15 +7,28 @@ #include <linux/libnvdimm.h> #include <asm/cacheflush.h> +#include <asm/dma-noncoherent.h> void arch_wb_cache_pmem(void *addr, size_t size) { +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.clean)) { + noncoherent_cache_ops.clean(virt_to_phys(addr), size); + return; + } +#endif ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); } EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); void arch_invalidate_pmem(void *addr, size_t size) { +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.inval)) { + noncoherent_cache_ops.inval(virt_to_phys(addr), size); + return; + } +#endif ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); } EXPORT_SYMBOL_GPL(arch_invalidate_pmem);