| Message ID | 20230619083517.415597-4-william.qiu@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Add initialization of clock for StarFive JH7110 SoC | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD d5e45e810e0e |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 6 and now 6 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 8 this patch: 8 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 20 this patch: 20 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 62 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On 19/06/2023 10:35, William Qiu wrote: > Add the quad spi controller node for the StarFive JH7110 SoC. > > Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com> > Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com> > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> > --- > .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++ > 2 files changed, 50 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 2a6d81609284..22212c1150f9 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -126,6 +126,38 @@ &i2c6 { > status = "okay"; > }; > > +&qspi { > + #address-cells = <1>; > + #size-cells = <0>; > + > + nor_flash: flash@0 { > + compatible = "jedec,spi-nor"; > + reg=<0>; Missing spaces. > + cdns,read-delay = <5>; > + spi-max-frequency = <12000000>; > + cdns,tshsl-ns = <1>; > + cdns,tsd2d-ns = <1>; > + cdns,tchsh-ns = <1>; > + cdns,tslch-ns = <1>; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + spl@0 { > + reg = <0x0 0x20000>; > + }; > + uboot@100000 { > + reg = <0x100000 0x300000>; > + }; > + data@f00000 { > + reg = <0xf00000 0x100000>; > + }; > + }; > + }; > +}; > + > &sysgpio { > i2c0_pins: i2c0-0 { > i2c-pins { > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 4c5fdb905da8..0b24f9e66e67 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -440,6 +440,24 @@ i2c6: i2c@12060000 { > status = "disabled"; > }; > > + qspi: spi@13010000 { > + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; > + reg = <0x0 0x13010000 0x0 0x10000 > + 0x0 0x21000000 0x0 0x400000>; This should be two items so <>, <>. Not one item. Best regards, Krzysztof
On 2023/6/19 20:20, Krzysztof Kozlowski wrote: > On 19/06/2023 10:35, William Qiu wrote: >> Add the quad spi controller node for the StarFive JH7110 SoC. >> >> Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com> >> Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com> >> Signed-off-by: William Qiu <william.qiu@starfivetech.com> >> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> >> --- >> .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++ >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++ >> 2 files changed, 50 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> index 2a6d81609284..22212c1150f9 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> @@ -126,6 +126,38 @@ &i2c6 { >> status = "okay"; >> }; >> >> +&qspi { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + nor_flash: flash@0 { >> + compatible = "jedec,spi-nor"; >> + reg=<0>; > > Missing spaces. > Will fix. >> + cdns,read-delay = <5>; >> + spi-max-frequency = <12000000>; >> + cdns,tshsl-ns = <1>; >> + cdns,tsd2d-ns = <1>; >> + cdns,tchsh-ns = <1>; >> + cdns,tslch-ns = <1>; >> + >> + partitions { >> + compatible = "fixed-partitions"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + spl@0 { >> + reg = <0x0 0x20000>; >> + }; >> + uboot@100000 { >> + reg = <0x100000 0x300000>; >> + }; >> + data@f00000 { >> + reg = <0xf00000 0x100000>; >> + }; >> + }; >> + }; >> +}; >> + >> &sysgpio { >> i2c0_pins: i2c0-0 { >> i2c-pins { >> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> index 4c5fdb905da8..0b24f9e66e67 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> @@ -440,6 +440,24 @@ i2c6: i2c@12060000 { >> status = "disabled"; >> }; >> >> + qspi: spi@13010000 { >> + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; >> + reg = <0x0 0x13010000 0x0 0x10000 >> + 0x0 0x21000000 0x0 0x400000>; > > This should be two items so <>, <>. Not one item. > > Best regards, > Krzysztof > Will fix. Thanks for taking time to review this patch series. Best reagards William
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 2a6d81609284..22212c1150f9 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -126,6 +126,38 @@ &i2c6 { status = "okay"; }; +&qspi { + #address-cells = <1>; + #size-cells = <0>; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg=<0>; + cdns,read-delay = <5>; + spi-max-frequency = <12000000>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + spl@0 { + reg = <0x0 0x20000>; + }; + uboot@100000 { + reg = <0x100000 0x300000>; + }; + data@f00000 { + reg = <0xf00000 0x100000>; + }; + }; + }; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins { diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..0b24f9e66e67 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -440,6 +440,24 @@ i2c6: i2c@12060000 { status = "disabled"; }; + qspi: spi@13010000 { + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000 + 0x0 0x21000000 0x0 0x400000>; + interrupts = <25>; + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_QSPI_AHB>, + <&syscrg JH7110_SYSCLK_QSPI_APB>; + clock-names = "ref", "ahb", "apb"; + resets = <&syscrg JH7110_SYSRST_QSPI_APB>, + <&syscrg JH7110_SYSRST_QSPI_AHB>, + <&syscrg JH7110_SYSRST_QSPI_REF>; + reset-names = "qspi", "qspi-ocp", "rstc_ref"; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + }; + syscrg: clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x0 0x13020000 0x0 0x10000>;