| Message ID | 20230607083139.3498788-3-ilkka@os.amperecomputing.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | perf: ampere: Add support for Ampere SoC PMUs | expand |
> -----Original Message----- > From: Ilkka Koskinen <ilkka@os.amperecomputing.com> > Sent: Wednesday, June 7, 2023 3:32 PM > To: Jonathan Corbet <corbet@lwn.net>; Will Deacon <will@kernel.org>; Mark > Rutland <mark.rutland@arm.com>; Besar Wicaksono > <bwicaksono@nvidia.com>; Suzuki K Poulose <suzuki.poulose@arm.com>; > Robin Murphy <robin.murphy@arm.com> > Cc: linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; Ilkka Koskinen <ilkka@os.amperecomputing.com> > Subject: [PATCH v3 2/4] perf: arm_cspmu: Support implementation specific > filters > > External email: Use caution opening links or attachments > > > Generic filters aren't used in all the platforms. Instead, the platforms > may use different means to filter events. Add support for implementation > specific filters. > > Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com> > --- > drivers/perf/arm_cspmu/arm_cspmu.c | 8 ++++++-- > drivers/perf/arm_cspmu/arm_cspmu.h | 4 ++++ > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c > b/drivers/perf/arm_cspmu/arm_cspmu.c > index f8b4a149eb88..72ca4f56347c 100644 > --- a/drivers/perf/arm_cspmu/arm_cspmu.c > +++ b/drivers/perf/arm_cspmu/arm_cspmu.c > @@ -122,6 +122,9 @@ > > static unsigned long arm_cspmu_cpuhp_state; > > +static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, > + struct hw_perf_event *hwc, u32 filter); > + > /* > * In CoreSight PMU architecture, all of the MMIO registers are 32-bit except > * counter register. The counter register can be implemented as 32-bit or 64- > bit > @@ -432,6 +435,7 @@ static int arm_cspmu_init_impl_ops(struct > arm_cspmu *cspmu) > CHECK_DEFAULT_IMPL_OPS(impl_ops, event_type); > CHECK_DEFAULT_IMPL_OPS(impl_ops, event_filter); > CHECK_DEFAULT_IMPL_OPS(impl_ops, event_attr_is_visible); > + CHECK_DEFAULT_IMPL_OPS(impl_ops, set_ev_filter); > > return 0; > } > @@ -798,7 +802,7 @@ static inline void arm_cspmu_set_event(struct > arm_cspmu *cspmu, > writel(hwc->config, cspmu->base0 + offset); > } > > -static inline void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, > +static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, > struct hw_perf_event *hwc, > u32 filter) > { > @@ -832,7 +836,7 @@ static void arm_cspmu_start(struct perf_event > *event, int pmu_flags) > arm_cspmu_set_cc_filter(cspmu, filter); > } else { > arm_cspmu_set_event(cspmu, hwc); > - arm_cspmu_set_ev_filter(cspmu, hwc, filter); > + cspmu->impl.ops.set_ev_filter(cspmu, hwc, filter); > } > > hwc->state = 0; > diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h > b/drivers/perf/arm_cspmu/arm_cspmu.h > index 51323b175a4a..f89ae2077164 100644 > --- a/drivers/perf/arm_cspmu/arm_cspmu.h > +++ b/drivers/perf/arm_cspmu/arm_cspmu.h > @@ -102,6 +102,10 @@ struct arm_cspmu_impl_ops { > u32 (*event_type)(const struct perf_event *event); > /* Decode filter value from configs */ > u32 (*event_filter)(const struct perf_event *event); > + /* Set event filter */ > + void (*set_ev_filter)(struct arm_cspmu *cspmu, > + struct hw_perf_event *hwc, > + u32 filter); > /* Hide/show unsupported events */ > umode_t (*event_attr_is_visible)(struct kobject *kobj, > struct attribute *attr, int unused); > -- > 2.40.1
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c index f8b4a149eb88..72ca4f56347c 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -122,6 +122,9 @@ static unsigned long arm_cspmu_cpuhp_state; +static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, + struct hw_perf_event *hwc, u32 filter); + /* * In CoreSight PMU architecture, all of the MMIO registers are 32-bit except * counter register. The counter register can be implemented as 32-bit or 64-bit @@ -432,6 +435,7 @@ static int arm_cspmu_init_impl_ops(struct arm_cspmu *cspmu) CHECK_DEFAULT_IMPL_OPS(impl_ops, event_type); CHECK_DEFAULT_IMPL_OPS(impl_ops, event_filter); CHECK_DEFAULT_IMPL_OPS(impl_ops, event_attr_is_visible); + CHECK_DEFAULT_IMPL_OPS(impl_ops, set_ev_filter); return 0; } @@ -798,7 +802,7 @@ static inline void arm_cspmu_set_event(struct arm_cspmu *cspmu, writel(hwc->config, cspmu->base0 + offset); } -static inline void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, +static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, struct hw_perf_event *hwc, u32 filter) { @@ -832,7 +836,7 @@ static void arm_cspmu_start(struct perf_event *event, int pmu_flags) arm_cspmu_set_cc_filter(cspmu, filter); } else { arm_cspmu_set_event(cspmu, hwc); - arm_cspmu_set_ev_filter(cspmu, hwc, filter); + cspmu->impl.ops.set_ev_filter(cspmu, hwc, filter); } hwc->state = 0; diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/arm_cspmu.h index 51323b175a4a..f89ae2077164 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.h +++ b/drivers/perf/arm_cspmu/arm_cspmu.h @@ -102,6 +102,10 @@ struct arm_cspmu_impl_ops { u32 (*event_type)(const struct perf_event *event); /* Decode filter value from configs */ u32 (*event_filter)(const struct perf_event *event); + /* Set event filter */ + void (*set_ev_filter)(struct arm_cspmu *cspmu, + struct hw_perf_event *hwc, + u32 filter); /* Hide/show unsupported events */ umode_t (*event_attr_is_visible)(struct kobject *kobj, struct attribute *attr, int unused);
Generic filters aren't used in all the platforms. Instead, the platforms may use different means to filter events. Add support for implementation specific filters. Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> --- drivers/perf/arm_cspmu/arm_cspmu.c | 8 ++++++-- drivers/perf/arm_cspmu/arm_cspmu.h | 4 ++++ 2 files changed, 10 insertions(+), 2 deletions(-)