diff mbox series

MIPS: mm: Remove special handling for OCTEON CPUs

Message ID 20230615093933.121329-1-tsbogend@alpha.franken.de (mailing list archive)
State Accepted
Commit 13e6b8122d448b07d16a3d9c0d0ab41d00a3f284
Headers show
Series MIPS: mm: Remove special handling for OCTEON CPUs | expand

Commit Message

Thomas Bogendoerfer June 15, 2023, 9:39 a.m. UTC 
Macro cpu_has_mips_r2_exec_hazard correctly handles OCTEON CPUs,
so we don't need the extra switch cases for them.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/mm/tlbex.c | 24 ++++--------------------
 1 file changed, 4 insertions(+), 20 deletions(-)

Comments

Thomas Bogendoerfer June 20, 2023, 12:50 p.m. UTC | #1 
On Thu, Jun 15, 2023 at 11:39:33AM +0200, Thomas Bogendoerfer wrote:
> Macro cpu_has_mips_r2_exec_hazard correctly handles OCTEON CPUs,
> so we don't need the extra switch cases for them.
> 
> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> ---
>  arch/mips/mm/tlbex.c | 24 ++++--------------------
>  1 file changed, 4 insertions(+), 20 deletions(-)

applied to mips-next.

Thomas.
diff mbox series

Patch

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 80e05ee98d62..8d514a9082c6 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2123,16 +2123,8 @@  static void build_r4000_tlb_load_handler(void)
 
 		uasm_i_tlbr(&p);
 
-		switch (current_cpu_type()) {
-		case CPU_CAVIUM_OCTEON:
-		case CPU_CAVIUM_OCTEON_PLUS:
-		case CPU_CAVIUM_OCTEON2:
-			break;
-		default:
-			if (cpu_has_mips_r2_exec_hazard)
-				uasm_i_ehb(&p);
-			break;
-		}
+		if (cpu_has_mips_r2_exec_hazard)
+			uasm_i_ehb(&p);
 
 		/* Examine  entrylo 0 or 1 based on ptr. */
 		if (use_bbit_insns()) {
@@ -2197,16 +2189,8 @@  static void build_r4000_tlb_load_handler(void)
 
 		uasm_i_tlbr(&p);
 
-		switch (current_cpu_type()) {
-		case CPU_CAVIUM_OCTEON:
-		case CPU_CAVIUM_OCTEON_PLUS:
-		case CPU_CAVIUM_OCTEON2:
-			break;
-		default:
-			if (cpu_has_mips_r2_exec_hazard)
-				uasm_i_ehb(&p);
-			break;
-		}
+		if (cpu_has_mips_r2_exec_hazard)
+			uasm_i_ehb(&p);
 
 		/* Examine  entrylo 0 or 1 based on ptr. */
 		if (use_bbit_insns()) {