| Message ID | 20230612210442.1805962-2-heiko.stuebner@vrull.eu (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Herbert Xu |
| Headers | show |
| Series | Implement GCM ghash using Zbc and Zbkb extensions | expand |
Hey Heiko, On Mon, Jun 12, 2023 at 11:04:39PM +0200, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@vrull.eu> > > Add handling for Zbc extension. > > Zbc provides instruction for carry-less multiplication. > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > --- > arch/riscv/Kconfig | 22 ++++++++++++++++++++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 4 files changed, 25 insertions(+) Plumbing into the hwprobe stuff would be nice, but that's not a requirement for getting stuff merged :) > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index a3d54cd14fca..754cd154eca5 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -523,6 +523,28 @@ config RISCV_ISA_ZBB > > If you don't know what to do here, say Y. > > +config TOOLCHAIN_HAS_ZBC > + bool > + default y > + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbc) > + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc) > + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900 > + depends on AS_IS_GNU > + > +config RISCV_ISA_ZBC > + bool "Zbc extension support for bit manipulation instructions" > + depends on TOOLCHAIN_HAS_ZBC > + depends on !XIP_KERNEL && MMU > + default y > + help > + Adds support to dynamically detect the presence of the ZBC Nit: s/ZBC/Zbc/ Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
On Mon, 12 Jun 2023 14:31:14 PDT (-0700), Conor Dooley wrote: > Hey Heiko, > > On Mon, Jun 12, 2023 at 11:04:39PM +0200, Heiko Stuebner wrote: >> From: Heiko Stuebner <heiko.stuebner@vrull.eu> >> >> Add handling for Zbc extension. >> >> Zbc provides instruction for carry-less multiplication. >> >> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> >> --- >> arch/riscv/Kconfig | 22 ++++++++++++++++++++++ >> arch/riscv/include/asm/hwcap.h | 1 + >> arch/riscv/kernel/cpu.c | 1 + >> arch/riscv/kernel/cpufeature.c | 1 + >> 4 files changed, 25 insertions(+) > > Plumbing into the hwprobe stuff would be nice, but that's not a > requirement for getting stuff merged :) IIRC we talked about this on IRC, but IMO we shouldn't require something be user visible for it to be merged in the kernel. >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >> index a3d54cd14fca..754cd154eca5 100644 >> --- a/arch/riscv/Kconfig >> +++ b/arch/riscv/Kconfig >> @@ -523,6 +523,28 @@ config RISCV_ISA_ZBB >> >> If you don't know what to do here, say Y. >> >> +config TOOLCHAIN_HAS_ZBC >> + bool >> + default y >> + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbc) >> + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc) >> + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900 >> + depends on AS_IS_GNU >> + >> +config RISCV_ISA_ZBC >> + bool "Zbc extension support for bit manipulation instructions" >> + depends on TOOLCHAIN_HAS_ZBC >> + depends on !XIP_KERNEL && MMU >> + default y >> + help >> + Adds support to dynamically detect the presence of the ZBC > > Nit: s/ZBC/Zbc/ > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Cheers, > Conor.
On Tue, Jun 20, 2023 at 12:09:28PM -0700, Palmer Dabbelt wrote: > On Mon, 12 Jun 2023 14:31:14 PDT (-0700), Conor Dooley wrote: > > Hey Heiko, > > > > On Mon, Jun 12, 2023 at 11:04:39PM +0200, Heiko Stuebner wrote: > > > From: Heiko Stuebner <heiko.stuebner@vrull.eu> > > > > > > Add handling for Zbc extension. > > > > > > Zbc provides instruction for carry-less multiplication. > > > > > > Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> > > > --- > > > arch/riscv/Kconfig | 22 ++++++++++++++++++++++ > > > arch/riscv/include/asm/hwcap.h | 1 + > > > arch/riscv/kernel/cpu.c | 1 + > > > arch/riscv/kernel/cpufeature.c | 1 + > > > 4 files changed, 25 insertions(+) > > > > Plumbing into the hwprobe stuff would be nice, but that's not a > > requirement for getting stuff merged :) > > IIRC we talked about this on IRC, but IMO we shouldn't require something be > user visible for it to be merged in the kernel. Yup, I asked you before replying since I wasn't sure what the "rules" were about hwprobe since it is so new.
On 6/20/23 13:09, Palmer Dabbelt wrote: > On Mon, 12 Jun 2023 14:31:14 PDT (-0700), Conor Dooley wrote: >> Hey Heiko, >> >> On Mon, Jun 12, 2023 at 11:04:39PM +0200, Heiko Stuebner wrote: >>> From: Heiko Stuebner <heiko.stuebner@vrull.eu> >>> >>> Add handling for Zbc extension. >>> >>> Zbc provides instruction for carry-less multiplication. >>> >>> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> >>> --- >>> arch/riscv/Kconfig | 22 ++++++++++++++++++++++ >>> arch/riscv/include/asm/hwcap.h | 1 + >>> arch/riscv/kernel/cpu.c | 1 + >>> arch/riscv/kernel/cpufeature.c | 1 + >>> 4 files changed, 25 insertions(+) >> >> Plumbing into the hwprobe stuff would be nice, but that's not a >> requirement for getting stuff merged :) > > IIRC we talked about this on IRC, but IMO we shouldn't require something > be user visible for it to be merged in the kernel. Note that exposing Zbc is potentially useful. We've got GCC and LLVM code that can detect and rewrite a bitwise CRC into clmul. Jeff
On Tue, 20 Jun 2023 12:37:00 PDT (-0700), Jeff Law wrote: > > > On 6/20/23 13:09, Palmer Dabbelt wrote: >> On Mon, 12 Jun 2023 14:31:14 PDT (-0700), Conor Dooley wrote: >>> Hey Heiko, >>> >>> On Mon, Jun 12, 2023 at 11:04:39PM +0200, Heiko Stuebner wrote: >>>> From: Heiko Stuebner <heiko.stuebner@vrull.eu> >>>> >>>> Add handling for Zbc extension. >>>> >>>> Zbc provides instruction for carry-less multiplication. >>>> >>>> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> >>>> --- >>>> arch/riscv/Kconfig | 22 ++++++++++++++++++++++ >>>> arch/riscv/include/asm/hwcap.h | 1 + >>>> arch/riscv/kernel/cpu.c | 1 + >>>> arch/riscv/kernel/cpufeature.c | 1 + >>>> 4 files changed, 25 insertions(+) >>> >>> Plumbing into the hwprobe stuff would be nice, but that's not a >>> requirement for getting stuff merged :) >> >> IIRC we talked about this on IRC, but IMO we shouldn't require something >> be user visible for it to be merged in the kernel. > Note that exposing Zbc is potentially useful. We've got GCC and LLVM > code that can detect and rewrite a bitwise CRC into clmul. Ya, there's another thread about adding it. IMO we should do so, just that we shouldn't gate kernel support on also sorting out the uABI as sometimes that's complicated. It's simple for this one, though, so I'm not opposed to taking it for the merge window if it shows up in the next day or two... > > Jeff
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a3d54cd14fca..754cd154eca5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -523,6 +523,28 @@ config RISCV_ISA_ZBB If you don't know what to do here, say Y. +config TOOLCHAIN_HAS_ZBC + bool + default y + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbc) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc) + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900 + depends on AS_IS_GNU + +config RISCV_ISA_ZBC + bool "Zbc extension support for bit manipulation instructions" + depends on TOOLCHAIN_HAS_ZBC + depends on !XIP_KERNEL && MMU + default y + help + Adds support to dynamically detect the presence of the ZBC + extension (carry-less multiplication) and enable its usage. + + The Zbc extension provides instructions clmul, clmulh and clmulr + to accelerate carry-less multiplications. + + If you don't know what to do here, say Y. + config RISCV_ISA_ZICBOM bool "Zicbom extension support for non-coherent DMA operation" depends on MMU diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e6c288ac4581..e48ac52b9174 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -47,6 +47,7 @@ #define RISCV_ISA_EXT_ZICBOZ 34 #define RISCV_ISA_EXT_SMAIA 35 #define RISCV_ISA_EXT_SSAIA 36 +#define RISCV_ISA_EXT_ZBC 37 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 637263f9a7b9..bbff98d4712a 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -188,6 +188,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index de2d16300f69..f46281f1e439 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,7 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);