| Message ID | 20230622011141.328029-2-ilkka@os.amperecomputing.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | perf: ampere: Add support for Ampere SoC PMUs | expand |
> -----Original Message----- > From: Ilkka Koskinen <ilkka@os.amperecomputing.com> > Sent: Thursday, June 22, 2023 8:12 AM > To: Will Deacon <will@kernel.org>; Robin Murphy <robin.murphy@arm.com>; > Besar Wicaksono <bwicaksono@nvidia.com>; Suzuki K Poulose > <suzuki.poulose@arm.com>; Mark Rutland <mark.rutland@arm.com> > Cc: Ilkka Koskinen <ilkka@os.amperecomputing.com>; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: [PATCH 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes > > External email: Use caution opening links or attachments > > > Split the 64-bit register accesses if 64-bit access is not supported > by the PMU. > > Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com> Thanks, Besar > --- > drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c > b/drivers/perf/arm_cspmu/arm_cspmu.c > index e2b7827c4563..0f517152cb4e 100644 > --- a/drivers/perf/arm_cspmu/arm_cspmu.c > +++ b/drivers/perf/arm_cspmu/arm_cspmu.c > @@ -696,7 +696,10 @@ static void arm_cspmu_write_counter(struct > perf_event *event, u64 val) > if (use_64b_counter_reg(cspmu)) { > offset = counter_offset(sizeof(u64), event->hw.idx); > > - writeq(val, cspmu->base1 + offset); > + if (cspmu->has_atomic_dword) > + writeq(val, cspmu->base1 + offset); > + else > + lo_hi_writeq(val, cspmu->base1 + offset); > } else { > offset = counter_offset(sizeof(u32), event->hw.idx); > > -- > 2.40.1
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c index e2b7827c4563..0f517152cb4e 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -696,7 +696,10 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val) if (use_64b_counter_reg(cspmu)) { offset = counter_offset(sizeof(u64), event->hw.idx); - writeq(val, cspmu->base1 + offset); + if (cspmu->has_atomic_dword) + writeq(val, cspmu->base1 + offset); + else + lo_hi_writeq(val, cspmu->base1 + offset); } else { offset = counter_offset(sizeof(u32), event->hw.idx);
Split the 64-bit register accesses if 64-bit access is not supported by the PMU. Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> --- drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)