| Message ID | 20230619-topic-sm8550-upstream-interconnect-mask-vote-v2-2-709474b151cc@linaro.org (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | interconnect: qcom: rpmh: sm8550: mask to send as vote | expand |
On 23.06.2023 14:50, Neil Armstrong wrote: > Set the proper enable_mask to nodes requiring such value > to be used instead of a bandwidth when voting. > > The masks were copied from the downstream implementation at [1]. > > [1] https://git.codelinaro.org/clo/la/kernel/msm-5.10/-/blob/KERNEL.PLATFORM.1.0.r2-05600-WAIPIOLE.0/drivers/interconnect/qcom/waipio.c > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/interconnect/qcom/sm8450.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c > index 2d7a8e7b85ec..e64c214b4020 100644 > --- a/drivers/interconnect/qcom/sm8450.c > +++ b/drivers/interconnect/qcom/sm8450.c > @@ -1337,6 +1337,7 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = { > > static struct qcom_icc_bcm bcm_acv = { > .name = "ACV", > + .enable_mask = 0x8, > .num_nodes = 1, > .nodes = { &ebi }, > }; > @@ -1349,6 +1350,7 @@ static struct qcom_icc_bcm bcm_ce0 = { > > static struct qcom_icc_bcm bcm_cn0 = { > .name = "CN0", > + .enable_mask = 0x1, > .keepalive = true, > .num_nodes = 55, > .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, > @@ -1383,6 +1385,7 @@ static struct qcom_icc_bcm bcm_cn0 = { > > static struct qcom_icc_bcm bcm_co0 = { > .name = "CO0", > + .enable_mask = 0x1, > .num_nodes = 2, > .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, > }; > @@ -1403,6 +1406,7 @@ static struct qcom_icc_bcm bcm_mm0 = { > > static struct qcom_icc_bcm bcm_mm1 = { > .name = "MM1", > + .enable_mask = 0x1, > .num_nodes = 12, > .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, > &qnm_camnoc_sf, &qnm_mdp, > @@ -1445,6 +1449,7 @@ static struct qcom_icc_bcm bcm_sh0 = { > > static struct qcom_icc_bcm bcm_sh1 = { > .name = "SH1", > + .enable_mask = 0x1, > .num_nodes = 7, > .nodes = { &alm_gpu_tcu, &alm_sys_tcu, > &qnm_nsp_gemnoc, &qnm_pcie, > @@ -1461,6 +1466,7 @@ static struct qcom_icc_bcm bcm_sn0 = { > > static struct qcom_icc_bcm bcm_sn1 = { > .name = "SN1", > + .enable_mask = 0x1, > .num_nodes = 4, > .nodes = { &qhm_gic, &qxm_pimem, > &xm_gic, &qns_gemnoc_gc }, > @@ -1492,6 +1498,7 @@ static struct qcom_icc_bcm bcm_sn7 = { > > static struct qcom_icc_bcm bcm_acv_disp = { > .name = "ACV", > + .enable_mask = 0x1, > .num_nodes = 1, > .nodes = { &ebi_disp }, > }; > @@ -1510,6 +1517,7 @@ static struct qcom_icc_bcm bcm_mm0_disp = { > > static struct qcom_icc_bcm bcm_mm1_disp = { > .name = "MM1", > + .enable_mask = 0x1, > .num_nodes = 3, > .nodes = { &qnm_mdp_disp, &qnm_rot_disp, > &qns_mem_noc_sf_disp }, > @@ -1523,6 +1531,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = { > > static struct qcom_icc_bcm bcm_sh1_disp = { > .name = "SH1", > + .enable_mask = 0x1, > .num_nodes = 1, > .nodes = { &qnm_pcie_disp }, > }; >
diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index 2d7a8e7b85ec..e64c214b4020 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1337,6 +1337,7 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = 0x8, .num_nodes = 1, .nodes = { &ebi }, }; @@ -1349,6 +1350,7 @@ static struct qcom_icc_bcm bcm_ce0 = { static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", + .enable_mask = 0x1, .keepalive = true, .num_nodes = 55, .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, @@ -1383,6 +1385,7 @@ static struct qcom_icc_bcm bcm_cn0 = { static struct qcom_icc_bcm bcm_co0 = { .name = "CO0", + .enable_mask = 0x1, .num_nodes = 2, .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, }; @@ -1403,6 +1406,7 @@ static struct qcom_icc_bcm bcm_mm0 = { static struct qcom_icc_bcm bcm_mm1 = { .name = "MM1", + .enable_mask = 0x1, .num_nodes = 12, .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_mdp, @@ -1445,6 +1449,7 @@ static struct qcom_icc_bcm bcm_sh0 = { static struct qcom_icc_bcm bcm_sh1 = { .name = "SH1", + .enable_mask = 0x1, .num_nodes = 7, .nodes = { &alm_gpu_tcu, &alm_sys_tcu, &qnm_nsp_gemnoc, &qnm_pcie, @@ -1461,6 +1466,7 @@ static struct qcom_icc_bcm bcm_sn0 = { static struct qcom_icc_bcm bcm_sn1 = { .name = "SN1", + .enable_mask = 0x1, .num_nodes = 4, .nodes = { &qhm_gic, &qxm_pimem, &xm_gic, &qns_gemnoc_gc }, @@ -1492,6 +1498,7 @@ static struct qcom_icc_bcm bcm_sn7 = { static struct qcom_icc_bcm bcm_acv_disp = { .name = "ACV", + .enable_mask = 0x1, .num_nodes = 1, .nodes = { &ebi_disp }, }; @@ -1510,6 +1517,7 @@ static struct qcom_icc_bcm bcm_mm0_disp = { static struct qcom_icc_bcm bcm_mm1_disp = { .name = "MM1", + .enable_mask = 0x1, .num_nodes = 3, .nodes = { &qnm_mdp_disp, &qnm_rot_disp, &qns_mem_noc_sf_disp }, @@ -1523,6 +1531,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = { static struct qcom_icc_bcm bcm_sh1_disp = { .name = "SH1", + .enable_mask = 0x1, .num_nodes = 1, .nodes = { &qnm_pcie_disp }, };
Set the proper enable_mask to nodes requiring such value to be used instead of a bandwidth when voting. The masks were copied from the downstream implementation at [1]. [1] https://git.codelinaro.org/clo/la/kernel/msm-5.10/-/blob/KERNEL.PLATFORM.1.0.r2-05600-WAIPIOLE.0/drivers/interconnect/qcom/waipio.c Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- drivers/interconnect/qcom/sm8450.c | 9 +++++++++ 1 file changed, 9 insertions(+)