| Message ID | 20230629221800.1478182-1-Henry.Wang@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | xen/arm: vgic: Add missing 'U' in VGIC_ICFG_MASK for shifted constant | expand |
On Fri, 30 Jun 2023, Henry Wang wrote: > With UBSAN on some arm64 platforms, e.g. FVP_Base_RevC-2xAEMvA, the > following splat will be printed while Dom0 is booting: > ``` > (XEN) ================================================================== > (XEN) UBSAN: Undefined behaviour in arch/arm/vgic.c:372:15 > (XEN) left shift of 1 by 31 places cannot be represented in type 'int' > (XEN) Xen WARN at common/ubsan/ubsan.c:172 > (XEN) ----[ Xen-4.18-unstable arm64 debug=y ubsan=y Not tainted ]---- > ``` > > This is because there is a device node in the device tree with 0xf > as the interrupts property. Example of the device tree node is shown > below: > ``` > ethernet@202000000 { > compatible = "smsc,lan91c111"; > reg = <0x2 0x2000000 0x10000>; > interrupts = <0xf>; > }; > ``` > and this value is passed to vgic_get_virq_type() as "index" then "intr" > in VGIC_ICFG_MASK. > > Add the missing 'U' in VGIC_ICFG_MASK as a fix, and this should also > addressing MISRA Rule 7.2: > > A "u" or "U" suffix shall be applied to all integer constants that > are represented in an unsigned type > > Signed-off-by: Henry Wang <Henry.Wang@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> > --- > This patch should be based on top of Julien's series > "xen/arm: Enable UBSAN support" to test. > --- > xen/arch/arm/vgic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c > index c61c68870c..97d6f61066 100644 > --- a/xen/arch/arm/vgic.c > +++ b/xen/arch/arm/vgic.c > @@ -358,7 +358,7 @@ void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) > } > } > > -#define VGIC_ICFG_MASK(intr) (1 << ((2 * ((intr) % 16)) + 1)) > +#define VGIC_ICFG_MASK(intr) (1U << ((2 * ((intr) % 16)) + 1)) > > /* The function should be called with the rank lock taken */ > static inline unsigned int vgic_get_virq_type(struct vcpu *v, int n, int index) > -- > 2.25.1 >
On 2023/6/30 07:03, Stefano Stabellini wrote: > On Fri, 30 Jun 2023, Henry Wang wrote: >> With UBSAN on some arm64 platforms, e.g. FVP_Base_RevC-2xAEMvA, the >> following splat will be printed while Dom0 is booting: >> ``` >> (XEN) ================================================================== >> (XEN) UBSAN: Undefined behaviour in arch/arm/vgic.c:372:15 >> (XEN) left shift of 1 by 31 places cannot be represented in type 'int' >> (XEN) Xen WARN at common/ubsan/ubsan.c:172 >> (XEN) ----[ Xen-4.18-unstable arm64 debug=y ubsan=y Not tainted ]---- >> ``` >> >> This is because there is a device node in the device tree with 0xf >> as the interrupts property. Example of the device tree node is shown >> below: >> ``` >> ethernet@202000000 { >> compatible = "smsc,lan91c111"; >> reg = <0x2 0x2000000 0x10000>; >> interrupts = <0xf>; >> }; >> ``` >> and this value is passed to vgic_get_virq_type() as "index" then "intr" >> in VGIC_ICFG_MASK. >> >> Add the missing 'U' in VGIC_ICFG_MASK as a fix, and this should also >> addressing MISRA Rule 7.2: >> >> A "u" or "U" suffix shall be applied to all integer constants that >> are represented in an unsigned type >> >> Signed-off-by: Henry Wang <Henry.Wang@arm.com> > Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> > > >> --- >> This patch should be based on top of Julien's series >> "xen/arm: Enable UBSAN support" to test. >> --- >> xen/arch/arm/vgic.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c >> index c61c68870c..97d6f61066 100644 >> --- a/xen/arch/arm/vgic.c >> +++ b/xen/arch/arm/vgic.c >> @@ -358,7 +358,7 @@ void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) >> } >> } >> >> -#define VGIC_ICFG_MASK(intr) (1 << ((2 * ((intr) % 16)) + 1)) >> +#define VGIC_ICFG_MASK(intr) (1U << ((2 * ((intr) % 16)) + 1)) >> >> /* The function should be called with the rank lock taken */ >> static inline unsigned int vgic_get_virq_type(struct vcpu *v, int n, int index) >> -- >> 2.25.1 >> Reviewed-by: Hongda Deng <hongda.deng@arm.com>
Hi, On 30/06/2023 00:03, Stefano Stabellini wrote: > On Fri, 30 Jun 2023, Henry Wang wrote: >> With UBSAN on some arm64 platforms, e.g. FVP_Base_RevC-2xAEMvA, the >> following splat will be printed while Dom0 is booting: >> ``` >> (XEN) ================================================================== >> (XEN) UBSAN: Undefined behaviour in arch/arm/vgic.c:372:15 >> (XEN) left shift of 1 by 31 places cannot be represented in type 'int' >> (XEN) Xen WARN at common/ubsan/ubsan.c:172 >> (XEN) ----[ Xen-4.18-unstable arm64 debug=y ubsan=y Not tainted ]---- >> ``` >> >> This is because there is a device node in the device tree with 0xf >> as the interrupts property. Example of the device tree node is shown >> below: >> ``` >> ethernet@202000000 { >> compatible = "smsc,lan91c111"; >> reg = <0x2 0x2000000 0x10000>; >> interrupts = <0xf>; >> }; >> ``` >> and this value is passed to vgic_get_virq_type() as "index" then "intr" >> in VGIC_ICFG_MASK. >> >> Add the missing 'U' in VGIC_ICFG_MASK as a fix, and this should also >> addressing MISRA Rule 7.2: >> >> A "u" or "U" suffix shall be applied to all integer constants that >> are represented in an unsigned type >> >> Signed-off-by: Henry Wang <Henry.Wang@arm.com> > > Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> It is now committed. Cheers,
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index c61c68870c..97d6f61066 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -358,7 +358,7 @@ void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) } } -#define VGIC_ICFG_MASK(intr) (1 << ((2 * ((intr) % 16)) + 1)) +#define VGIC_ICFG_MASK(intr) (1U << ((2 * ((intr) % 16)) + 1)) /* The function should be called with the rank lock taken */ static inline unsigned int vgic_get_virq_type(struct vcpu *v, int n, int index)
With UBSAN on some arm64 platforms, e.g. FVP_Base_RevC-2xAEMvA, the following splat will be printed while Dom0 is booting: ``` (XEN) ================================================================== (XEN) UBSAN: Undefined behaviour in arch/arm/vgic.c:372:15 (XEN) left shift of 1 by 31 places cannot be represented in type 'int' (XEN) Xen WARN at common/ubsan/ubsan.c:172 (XEN) ----[ Xen-4.18-unstable arm64 debug=y ubsan=y Not tainted ]---- ``` This is because there is a device node in the device tree with 0xf as the interrupts property. Example of the device tree node is shown below: ``` ethernet@202000000 { compatible = "smsc,lan91c111"; reg = <0x2 0x2000000 0x10000>; interrupts = <0xf>; }; ``` and this value is passed to vgic_get_virq_type() as "index" then "intr" in VGIC_ICFG_MASK. Add the missing 'U' in VGIC_ICFG_MASK as a fix, and this should also addressing MISRA Rule 7.2: A "u" or "U" suffix shall be applied to all integer constants that are represented in an unsigned type Signed-off-by: Henry Wang <Henry.Wang@arm.com> --- This patch should be based on top of Julien's series "xen/arm: Enable UBSAN support" to test. --- xen/arch/arm/vgic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)