| Message ID | 20230703081215.55252-1-fbarrat@linux.ibm.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Fix PSIHB interrupts init PQ state | expand |
On 3/7/23 10:12, Frederic Barrat wrote: > Frederic Barrat (2): > pnv/xive: Add property on xive sources to define PQ state on reset > pnv/psi: Initialize the PSIHB interrupts to match hardware Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/3/23 05:12, Frederic Barrat wrote: > On P9 and 10, the real hardware defines the PQ state of the PSIHB > interrupts to be 0b00. Qemu defaults to 0b01. > > It doesn't matter to skiboot, which doesn't rely on it and explicitly > masks the interrupts during intialization. But this patch fixes it, > just in case some other hypervisor checks it. > > Changelog: > v2: rename property/struct member > rebase to Daniel's ppc-next branch > > > Frederic Barrat (2): > pnv/xive: Add property on xive sources to define PQ state on reset > pnv/psi: Initialize the PSIHB interrupts to match hardware > > hw/intc/xive.c | 8 ++++++-- > hw/ppc/pnv_psi.c | 2 ++ > include/hw/ppc/xive.h | 1 + > 3 files changed, 9 insertions(+), 2 deletions(-) >
On P9 and 10, the real hardware defines the PQ state of the PSIHB interrupts to be 0b00. Qemu defaults to 0b01. It doesn't matter to skiboot, which doesn't rely on it and explicitly masks the interrupts during intialization. But this patch fixes it, just in case some other hypervisor checks it. Changelog: v2: rename property/struct member rebase to Daniel's ppc-next branch Frederic Barrat (2): pnv/xive: Add property on xive sources to define PQ state on reset pnv/psi: Initialize the PSIHB interrupts to match hardware hw/intc/xive.c | 8 ++++++-- hw/ppc/pnv_psi.c | 2 ++ include/hw/ppc/xive.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-)