| Message ID | 20230706024528.40065-1-joel@jms.id.au (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ppc/pnv: Log all unimp warnings with similar message | expand |
On 7/6/23 04:45, Joel Stanley wrote: > Add the function name so there's an indication as to where the message > is coming from. Change all prints to use the offset instead of the > address. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > Happy to use the address instead of the offset (or print both), but I > like the idea of being consistent. > --- > hw/ppc/pnv_core.c | 34 ++++++++++++++++++---------------- > 1 file changed, 18 insertions(+), 16 deletions(-) > > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index ffbc29cbf4f9..3eb95670d6a3 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -85,8 +85,8 @@ static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, > val = 0x24f000000000000ull; > break; > default: > - qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", > - addr); > + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, > + offset); > } > > return val; > @@ -95,8 +95,10 @@ static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, > static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, > unsigned int width) > { > - qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", > - addr); > + uint32_t offset = addr >> 3; > + > + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, > + offset); > } > > static const MemoryRegionOps pnv_core_power8_xscom_ops = { > @@ -140,8 +142,8 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, > val = 0; > break; > default: > - qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", > - addr); > + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, > + offset); > } > > return val; > @@ -157,8 +159,8 @@ static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, > case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: > break; > default: > - qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", > - addr); > + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, > + offset); > } > } > > @@ -189,8 +191,8 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr, > val = 0; > break; > default: > - qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", > - addr); > + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, > + offset); > } > > return val; > @@ -203,8 +205,8 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr, > > switch (offset) { > default: > - qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", > - addr); > + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, > + offset); > } > } > > @@ -421,7 +423,7 @@ static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr, > val = 0; > break; > default: > - qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__, > + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, > offset); > } > > @@ -438,7 +440,7 @@ static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, > case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ > break; > default: > - qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, > + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, > offset); > } > } > @@ -465,7 +467,7 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, > > switch (offset) { > default: > - qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__, > + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, > offset); > } > > @@ -479,7 +481,7 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, > > switch (offset) { > default: > - qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, > + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, > offset); > } > }
On 6/7/23 04:45, Joel Stanley wrote: > Add the function name so there's an indication as to where the message > is coming from. Change all prints to use the offset instead of the > address. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > Happy to use the address instead of the offset (or print both), but I > like the idea of being consistent. > --- > hw/ppc/pnv_core.c | 34 ++++++++++++++++++---------------- > 1 file changed, 18 insertions(+), 16 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/5/23 23:45, Joel Stanley wrote: > Add the function name so there's an indication as to where the message > is coming from. Change all prints to use the offset instead of the > address. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > Happy to use the address instead of the offset (or print both), but I > like the idea of being consistent. > --- > hw/ppc/pnv_core.c | 34 ++++++++++++++++++---------------- > 1 file changed, 18 insertions(+), 16 deletions(-) > > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index ffbc29cbf4f9..3eb95670d6a3 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -85,8 +85,8 @@ static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, > val = 0x24f000000000000ull; > break; > default: > - qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", > - addr); > + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, > + offset); > } > > return val; > @@ -95,8 +95,10 @@ static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, > static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, > unsigned int width) > { > - qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", > - addr); > + uint32_t offset = addr >> 3; > + > + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, > + offset); > } > > static const MemoryRegionOps pnv_core_power8_xscom_ops = { > @@ -140,8 +142,8 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, > val = 0; > break; > default: > - qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", > - addr); > + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, > + offset); > } > > return val; > @@ -157,8 +159,8 @@ static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, > case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: > break; > default: > - qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", > - addr); > + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, > + offset); > } > } > > @@ -189,8 +191,8 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr, > val = 0; > break; > default: > - qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", > - addr); > + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, > + offset); > } > > return val; > @@ -203,8 +205,8 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr, > > switch (offset) { > default: > - qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", > - addr); > + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, > + offset); > } > } > > @@ -421,7 +423,7 @@ static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr, > val = 0; > break; > default: > - qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__, > + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, > offset); > } > > @@ -438,7 +440,7 @@ static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, > case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ > break; > default: > - qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, > + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, > offset); > } > } > @@ -465,7 +467,7 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, > > switch (offset) { > default: > - qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__, > + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, > offset); > } > > @@ -479,7 +481,7 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, > > switch (offset) { > default: > - qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, > + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, > offset); > } > }
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index ffbc29cbf4f9..3eb95670d6a3 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -85,8 +85,8 @@ static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, val = 0x24f000000000000ull; break; default: - qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", - addr); + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, + offset); } return val; @@ -95,8 +95,10 @@ static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, unsigned int width) { - qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", - addr); + uint32_t offset = addr >> 3; + + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, + offset); } static const MemoryRegionOps pnv_core_power8_xscom_ops = { @@ -140,8 +142,8 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, val = 0; break; default: - qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", - addr); + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, + offset); } return val; @@ -157,8 +159,8 @@ static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: break; default: - qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", - addr); + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, + offset); } } @@ -189,8 +191,8 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr, val = 0; break; default: - qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", - addr); + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, + offset); } return val; @@ -203,8 +205,8 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr, switch (offset) { default: - qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", - addr); + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, + offset); } } @@ -421,7 +423,7 @@ static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr, val = 0; break; default: - qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__, + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, offset); } @@ -438,7 +440,7 @@ static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ break; default: - qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, offset); } } @@ -465,7 +467,7 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, switch (offset) { default: - qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__, + qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, offset); } @@ -479,7 +481,7 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, switch (offset) { default: - qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, offset); } }
Add the function name so there's an indication as to where the message is coming from. Change all prints to use the offset instead of the address. Signed-off-by: Joel Stanley <joel@jms.id.au> --- Happy to use the address instead of the offset (or print both), but I like the idea of being consistent. --- hw/ppc/pnv_core.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-)