diff mbox series

[v2] arm64: dts: imx8ulp-evk: add caam jr

Message ID DU2PR04MB86300C782DC7637C469599EC9526A@DU2PR04MB8630.eurprd04.prod.outlook.com (mailing list archive)
State New, archived
Headers show
Series [v2] arm64: dts: imx8ulp-evk: add caam jr | expand

Commit Message

Pankaj Gupta June 26, 2023, 4:46 a.m. UTC
V2: Changed the email subject line.
------------------------------------------------


Add crypto node in device tree for:
- CAAM job-ring

Signed-off-by: Varun Sethi <v.sethi@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

Comments

Pankaj Gupta July 10, 2023, 5:27 a.m. UTC | #1
Hi All,

Gentle reminder. Please review this patch.

Thanks.
Pankaj

> -----Original Message-----
> From: Pankaj Gupta <pankaj.gupta@nxp.com>
> Sent: Monday, June 26, 2023 10:17 AM
> To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> conor+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx <linux-
> imx@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> Subject: [PATCH v2] arm64: dts: imx8ulp-evk: add caam jr
> 
> V2: Changed the email subject line.
> ------------------------------------------------
> 
> 
> Add crypto node in device tree for:
> - CAAM job-ring
> 
> Signed-off-by: Varun Sethi <v.sethi@nxp.com>
> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32
> ++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> index 32193a43ff49..ce8de81cac9a 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> @@ -207,6 +207,38 @@ pcc3: clock-controller@292d0000 {
>  				#reset-cells = <1>;
>  			};
> 
> +			crypto: crypto@292e0000 {
> +				compatible = "fsl,sec-v4.0";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x292e0000 0x10000>;
> +				ranges = <0 0x292e0000 0x10000>;
> +
> +				sec_jr0: jr@1000 {
> +					compatible = "fsl,sec-v4.0-job-ring";
> +					reg = <0x1000 0x1000>;
> +					interrupts = <GIC_SPI 82
> IRQ_TYPE_LEVEL_HIGH>;
> +				};
> +
> +				sec_jr1: jr@2000 {
> +					compatible = "fsl,sec-v4.0-job-ring";
> +					reg = <0x2000 0x1000>;
> +					interrupts = <GIC_SPI 82
> IRQ_TYPE_LEVEL_HIGH>;
> +				};
> +
> +				sec_jr2: jr@3000 {
> +					compatible = "fsl,sec-v4.0-job-ring";
> +					reg = <0x3000 0x1000>;
> +					interrupts = <GIC_SPI 82
> IRQ_TYPE_LEVEL_HIGH>;
> +				};
> +
> +				sec_jr3: jr@4000 {
> +					compatible = "fsl,sec-v4.0-job-ring";
> +					reg = <0x4000 0x1000>;
> +					interrupts = <GIC_SPI 82
> IRQ_TYPE_LEVEL_HIGH>;
> +				};
> +			};
> +
>  			tpm5: tpm@29340000 {
>  				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-
> tpm";
>  				reg = <0x29340000 0x1000>;
> --
> 2.34.1
Krzysztof Kozlowski July 10, 2023, 6:23 a.m. UTC | #2
On 10/07/2023 07:27, Pankaj Gupta wrote:
> Hi All,
> 
> Gentle reminder. Please review this patch.
> 
> Thanks.
> Pankaj
> 
>> -----Original Message-----
>> From: Pankaj Gupta <pankaj.gupta@nxp.com>
>> Sent: Monday, June 26, 2023 10:17 AM
>> To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
>> conor+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de;
>> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx <linux-
>> imx@nxp.com>; devicetree@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
>> Cc: Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
>> Subject: [PATCH v2] arm64: dts: imx8ulp-evk: add caam jr
>>
>> V2: Changed the email subject line.
>> ------------------------------------------------
>>
>>

That's not a place for changelog. It goes after --- .

>> Add crypto node in device tree for:
>> - CAAM job-ring
>>
>> Signed-off-by: Varun Sethi <v.sethi@nxp.com>
>> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
>> ---
>>  arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32
>> ++++++++++++++++++++++
>>  1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
>> b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
>> index 32193a43ff49..ce8de81cac9a 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
>> @@ -207,6 +207,38 @@ pcc3: clock-controller@292d0000 {
>>  				#reset-cells = <1>;
>>  			};
>>
>> +			crypto: crypto@292e0000 {
>> +				compatible = "fsl,sec-v4.0";
>> +				#address-cells = <1>;
>> +				#size-cells = <1>;
>> +				reg = <0x292e0000 0x10000>;

reg is after compatible

>> +				ranges = <0 0x292e0000 0x10000>;

ranges should be third.

>> +


Best regards,
Krzysztof
Krzysztof Kozlowski July 10, 2023, 6:25 a.m. UTC | #3
On 10/07/2023 07:27, Pankaj Gupta wrote:
> Hi All,
> 
> Gentle reminder. Please review this patch.

Why do you ping just after the merge window? You sent the patch during
or just before the merge window when SoC's maintainer tree is obviously
closed, so why so impatient? Instead try to adjust to Linux kernel
process instead of pinging us...

Best regards,
Krzysztof
Shawn Guo July 18, 2023, 2:07 a.m. UTC | #4
On Mon, Jun 26, 2023 at 04:46:46AM +0000, Pankaj Gupta wrote:
> V2: Changed the email subject line.
> ------------------------------------------------
> 
> 
> Add crypto node in device tree for:
> - CAAM job-ring
> 
> Signed-off-by: Varun Sethi <v.sethi@nxp.com>
> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32 ++++++++++++++++++++++
>  1 file changed, 32 insertions(+)

The patch only changes imx8ulp SoC instead of imx8ulp-evk board,
so the patch subject should be:

  arm64: dts: imx8ulp: ...

Shawn
Pankaj Gupta July 18, 2023, 4:50 a.m. UTC | #5
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Tuesday, July 18, 2023 7:38 AM
> To: Pankaj Gupta <pankaj.gupta@nxp.com>
> Cc: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> conor+dt@kernel.org; s.hauer@pengutronix.de; kernel@pengutronix.de;
> festevam@gmail.com; dl-linux-imx <linux-imx@nxp.com>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Varun Sethi <V.Sethi@nxp.com>
> Subject: [EXT] Re: [PATCH v2] arm64: dts: imx8ulp-evk: add caam jr
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
> 
> 
> On Mon, Jun 26, 2023 at 04:46:46AM +0000, Pankaj Gupta wrote:
> > V2: Changed the email subject line.
> > ------------------------------------------------
> >
> >
> > Add crypto node in device tree for:
> > - CAAM job-ring
> >
> > Signed-off-by: Varun Sethi <v.sethi@nxp.com>
> > Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32
> > ++++++++++++++++++++++
> >  1 file changed, 32 insertions(+)
> 
> The patch only changes imx8ulp SoC instead of imx8ulp-evk board, so the
> patch subject should be:
> 
>   arm64: dts: imx8ulp: ...
> [Accepted]. Correct this in next version.

> Shawn
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 32193a43ff49..ce8de81cac9a 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -207,6 +207,38 @@  pcc3: clock-controller@292d0000 {
 				#reset-cells = <1>;
 			};
 
+			crypto: crypto@292e0000 {
+				compatible = "fsl,sec-v4.0";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x292e0000 0x10000>;
+				ranges = <0 0x292e0000 0x10000>;
+
+				sec_jr0: jr@1000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x1000 0x1000>;
+					interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr1: jr@2000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x2000 0x1000>;
+					interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr2: jr@3000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x3000 0x1000>;
+					interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr3: jr@4000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x4000 0x1000>;
+					interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+			};
+
 			tpm5: tpm@29340000 {
 				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
 				reg = <0x29340000 0x1000>;