diff mbox series

ARM: dts: stm32: re-add CAN support on stm32f746

Message ID 20230704173317.590190-1-dario.binacchi@amarulasolutions.com (mailing list archive)
State New, archived
Headers show
Series ARM: dts: stm32: re-add CAN support on stm32f746 | expand

Commit Message

Dario Binacchi July 4, 2023, 5:33 p.m. UTC 
The revert commit 36a6418bb1259 ("Revert "ARM: dts: stm32: add CAN support
on stm32f746"") prevented parsing errors due to the lack of CAN3 binding.

Now that the binding definition for CAN3 is available in the mainline
thanks to commit 8f3ef556f8e1a ("dt-bindings: mfd: stm32f7: Add binding
definition for CAN3"), we can re-add the CAN support and make the driver
usable again.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---

 arch/arm/boot/dts/st/stm32f746.dtsi | 47 +++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

Comments

Alexandre TORGUE July 11, 2023, 9:54 a.m. UTC | #1 
Hi Dario

On 7/4/23 19:33, Dario Binacchi wrote:
> The revert commit 36a6418bb1259 ("Revert "ARM: dts: stm32: add CAN support
> on stm32f746"") prevented parsing errors due to the lack of CAN3 binding.
> 
> Now that the binding definition for CAN3 is available in the mainline
> thanks to commit 8f3ef556f8e1a ("dt-bindings: mfd: stm32f7: Add binding
> definition for CAN3"), we can re-add the CAN support and make the driver
> usable again.
> 
> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
> ---
> 

...

> +		};
> +
> +		can2: can@40006800 {
> +			compatible = "st,stm32f4-bxcan";
> +			reg = <0x40006800 0x200>;
> +			iterrupts = <63>, <64>, <65>, <66>;

I modified this (bad) line and applied the patch on stm32-next.

br
Alex


> +			interrupt-names = "tx", "rx0", "rx1", "sce";
> +			resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
> +			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
> +			st,can-secondary;
> +			st,gcan = <&gcan1>;
> +			status = "disabled";
> +		};
> +
>   		cec: cec@40006c00 {
>   			compatible = "st,stm32-cec";
>   			reg = <0x40006C00 0x400>;
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi
index d1802efd067c..bfff1a58bf3d 100644
--- a/arch/arm/boot/dts/st/stm32f746.dtsi
+++ b/arch/arm/boot/dts/st/stm32f746.dtsi
@@ -257,6 +257,23 @@  rtc: rtc@40002800 {
 			status = "disabled";
 		};
 
+		can3: can@40003400 {
+			compatible = "st,stm32f4-bxcan";
+			reg = <0x40003400 0x200>;
+			interrupts = <104>, <105>, <106>, <107>;
+			interrupt-names = "tx", "rx0", "rx1", "sce";
+			resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
+			st,gcan = <&gcan3>;
+			status = "disabled";
+		};
+
+		gcan3: gcan@40003600 {
+			compatible = "st,stm32f4-gcan", "syscon";
+			reg = <0x40003600 0x200>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
+		};
+
 		usart2: serial@40004400 {
 			compatible = "st,stm32f7-uart";
 			reg = <0x40004400 0x400>;
@@ -337,6 +354,36 @@  i2c4: i2c@40006000 {
 			status = "disabled";
 		};
 
+		can1: can@40006400 {
+			compatible = "st,stm32f4-bxcan";
+			reg = <0x40006400 0x200>;
+			interrupts = <19>, <20>, <21>, <22>;
+			interrupt-names = "tx", "rx0", "rx1", "sce";
+			resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
+			st,can-primary;
+			st,gcan = <&gcan1>;
+			status = "disabled";
+		};
+
+		gcan1: gcan@40006600 {
+			compatible = "st,stm32f4-gcan", "syscon";
+			reg = <0x40006600 0x200>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
+		};
+
+		can2: can@40006800 {
+			compatible = "st,stm32f4-bxcan";
+			reg = <0x40006800 0x200>;
+			iterrupts = <63>, <64>, <65>, <66>;
+			interrupt-names = "tx", "rx0", "rx1", "sce";
+			resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
+			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
+			st,can-secondary;
+			st,gcan = <&gcan1>;
+			status = "disabled";
+		};
+
 		cec: cec@40006c00 {
 			compatible = "st,stm32-cec";
 			reg = <0x40006C00 0x400>;