| Message ID | 20230711133348.151383-3-parri.andrea@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | riscv,mmio: I/O barriers fixes and cleanups | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 06c2afb862f9 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 4 and now 4 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 2662 this patch: 2662 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 14984 this patch: 14984 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 78 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | fail | Build failed |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | fail | Build failed |
On Tue, Jul 11, 2023 at 03:33:48PM +0200, Andrea Parri wrote: > The current implementation of readX(), writeX() and their "relaxed" > variants, readX_relaxed() and writeX_relaxed(), matches the generic > implementation; remove the redundant code. > > No functional change intended. > > Signed-off-by: Andrea Parri <parri.andrea@gmail.com> This fails to build for (64-bit, I didn't check 32-bit) nommu: arch/riscv/include/asm/timex.h:20:16: error: implicit declaration of function 'readq_relaxed' [-Werror=implicit-function-declaration] include/asm-generic/io.h:342:23: error: conflicting types for 'readq_relaxed'; have 'u64(const volatile void *)' {aka 'long long unsigned int(const volatile void *)'} Cheers, Conor. > --- > arch/riscv/include/asm/mmio.h | 68 ++++------------------------------- > 1 file changed, 6 insertions(+), 62 deletions(-) > > diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h > index 4c58ee7f95ecf..116b898fe969d 100644 > --- a/arch/riscv/include/asm/mmio.h > +++ b/arch/riscv/include/asm/mmio.h > @@ -80,72 +80,16 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) > #endif > > /* > - * Unordered I/O memory access primitives. These are even more relaxed than > - * the relaxed versions, as they don't even order accesses between successive > - * operations to the I/O regions. > - */ > -#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; }) > -#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) > -#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) > - > -#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c))) > -#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c))) > -#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c))) > - > -#ifdef CONFIG_64BIT > -#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) > -#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c))) > -#endif > - > -/* > - * Relaxed I/O memory access primitives. These follow the Device memory > - * ordering rules but do not guarantee any ordering relative to Normal memory > - * accesses. These are defined to order the indicated access (either a read or > - * write) with all other I/O memory accesses to the same peripheral. Since the > - * platform specification defines that all I/O regions are strongly ordered on > - * channel 0, no explicit fences are required to enforce this ordering. > - */ > -/* FIXME: These are now the same as asm-generic */ > -#define __io_rbr() do {} while (0) > -#define __io_rar() do {} while (0) > -#define __io_rbw() do {} while (0) > -#define __io_raw() do {} while (0) > - > -#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; }) > -#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; }) > -#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; }) > - > -#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); }) > -#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); }) > -#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); }) > - > -#ifdef CONFIG_64BIT > -#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; }) > -#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); }) > -#endif > - > -/* > - * I/O memory access primitives. Reads are ordered relative to any following > - * Normal memory read and delay() loop. Writes are ordered relative to any > - * prior Normal memory write. The memory barriers here are necessary as RISC-V > - * doesn't define any ordering between the memory space and the I/O space. > + * I/O barriers > + * > + * See Documentation/memory-barriers.txt, "Kernel I/O barrier effects". > + * > + * Assume that each I/O region is strongly ordered on channel 0, following the > + * RISC-V Platform Specification, "OS-A Common Requirements". > */ > #define __io_br() do {} while (0) > #define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); }) > #define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) > #define __io_aw() mmiowb_set_pending() > > -#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) > -#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; }) > -#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; }) > - > -#define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); }) > -#define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); }) > -#define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); }) > - > -#ifdef CONFIG_64BIT > -#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; }) > -#define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); }) > -#endif > - > #endif /* _ASM_RISCV_MMIO_H */ > -- > 2.34.1 >
On Wed, Jul 12, 2023 at 08:05:16AM +0100, Conor Dooley wrote: > On Tue, Jul 11, 2023 at 03:33:48PM +0200, Andrea Parri wrote: > > The current implementation of readX(), writeX() and their "relaxed" > > variants, readX_relaxed() and writeX_relaxed(), matches the generic > > implementation; remove the redundant code. > > > > No functional change intended. > > > > Signed-off-by: Andrea Parri <parri.andrea@gmail.com> > > This fails to build for (64-bit, I didn't check 32-bit) nommu: > arch/riscv/include/asm/timex.h:20:16: error: implicit declaration of function 'readq_relaxed' [-Werror=implicit-function-declaration] > include/asm-generic/io.h:342:23: error: conflicting types for 'readq_relaxed'; have 'u64(const volatile void *)' {aka 'long long unsigned int(const volatile void *)'} Thank you for the report, Conor. Looking at it. Andrea
diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index 4c58ee7f95ecf..116b898fe969d 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -80,72 +80,16 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #endif /* - * Unordered I/O memory access primitives. These are even more relaxed than - * the relaxed versions, as they don't even order accesses between successive - * operations to the I/O regions. - */ -#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; }) -#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) -#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) - -#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c))) -#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c))) -#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c))) - -#ifdef CONFIG_64BIT -#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) -#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c))) -#endif - -/* - * Relaxed I/O memory access primitives. These follow the Device memory - * ordering rules but do not guarantee any ordering relative to Normal memory - * accesses. These are defined to order the indicated access (either a read or - * write) with all other I/O memory accesses to the same peripheral. Since the - * platform specification defines that all I/O regions are strongly ordered on - * channel 0, no explicit fences are required to enforce this ordering. - */ -/* FIXME: These are now the same as asm-generic */ -#define __io_rbr() do {} while (0) -#define __io_rar() do {} while (0) -#define __io_rbw() do {} while (0) -#define __io_raw() do {} while (0) - -#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; }) -#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; }) -#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; }) - -#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); }) -#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); }) -#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); }) - -#ifdef CONFIG_64BIT -#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; }) -#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); }) -#endif - -/* - * I/O memory access primitives. Reads are ordered relative to any following - * Normal memory read and delay() loop. Writes are ordered relative to any - * prior Normal memory write. The memory barriers here are necessary as RISC-V - * doesn't define any ordering between the memory space and the I/O space. + * I/O barriers + * + * See Documentation/memory-barriers.txt, "Kernel I/O barrier effects". + * + * Assume that each I/O region is strongly ordered on channel 0, following the + * RISC-V Platform Specification, "OS-A Common Requirements". */ #define __io_br() do {} while (0) #define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); }) #define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) #define __io_aw() mmiowb_set_pending() -#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) -#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; }) -#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; }) - -#define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); }) -#define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); }) -#define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); }) - -#ifdef CONFIG_64BIT -#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; }) -#define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); }) -#endif - #endif /* _ASM_RISCV_MMIO_H */
The current implementation of readX(), writeX() and their "relaxed" variants, readX_relaxed() and writeX_relaxed(), matches the generic implementation; remove the redundant code. No functional change intended. Signed-off-by: Andrea Parri <parri.andrea@gmail.com> --- arch/riscv/include/asm/mmio.h | 68 ++++------------------------------- 1 file changed, 6 insertions(+), 62 deletions(-)