| Message ID | 20230720054100.9940-5-manivannan.sadhasivam@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | viresh kumar |
| Headers | show |
| Series | UFS: Add OPP and interconnect support | expand |
On 20-07-23, 11:10, Manivannan Sadhasivam wrote: > Minimum frequency of the "ice_core_clk" should be 75MHz as specified in the > downstream vendor devicetree. So fix it! > > https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LA.UM.7.3.r1-09300-sdm845.0/arch/arm64/boot/dts/qcom/sdm845.dtsi > > Fixes: 433f9a57298f ("arm64: dts: sdm845: add Inline Crypto Engine registers and clock") > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 9ed74bf72d05..89520a9fe1e3 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -2614,7 +2614,7 @@ ufs_mem_hc: ufshc@1d84000 { > <0 0>, > <0 0>, > <0 0>, > - <0 300000000>; > + <75000000 300000000>; > > status = "disabled"; > }; Please keep new feature and fixes like this in separate series. This could be merged directly in the currently ongoing kernel rc and doesn't need to wait for this series. Or at least keep the commit at the top, so another maintainer can simply pick it.
On Fri, Jul 21, 2023 at 12:48:01PM +0530, Viresh Kumar wrote: > On 20-07-23, 11:10, Manivannan Sadhasivam wrote: > > Minimum frequency of the "ice_core_clk" should be 75MHz as specified in the > > downstream vendor devicetree. So fix it! > > > > https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LA.UM.7.3.r1-09300-sdm845.0/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > > Fixes: 433f9a57298f ("arm64: dts: sdm845: add Inline Crypto Engine registers and clock") > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > index 9ed74bf72d05..89520a9fe1e3 100644 > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > @@ -2614,7 +2614,7 @@ ufs_mem_hc: ufshc@1d84000 { > > <0 0>, > > <0 0>, > > <0 0>, > > - <0 300000000>; > > + <75000000 300000000>; > > > > status = "disabled"; > > }; > > Please keep new feature and fixes like this in separate series. This > could be merged directly in the currently ongoing kernel rc and > doesn't need to wait for this series. > > Or at least keep the commit at the top, so another maintainer can > simply pick it. > That's what I did. This patch and previous patch are the fixes patches, so they are posted on top of other dts patches to be merged separately if required. - Mani > -- > viresh
On Fri, Jul 21, 2023 at 05:27:31PM +0530, Manivannan Sadhasivam wrote: > On Fri, Jul 21, 2023 at 12:48:01PM +0530, Viresh Kumar wrote: > > On 20-07-23, 11:10, Manivannan Sadhasivam wrote: > > > Minimum frequency of the "ice_core_clk" should be 75MHz as specified in the > > > downstream vendor devicetree. So fix it! > > > > > > https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LA.UM.7.3.r1-09300-sdm845.0/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > > > > Fixes: 433f9a57298f ("arm64: dts: sdm845: add Inline Crypto Engine registers and clock") > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > --- > > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > index 9ed74bf72d05..89520a9fe1e3 100644 > > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > @@ -2614,7 +2614,7 @@ ufs_mem_hc: ufshc@1d84000 { > > > <0 0>, > > > <0 0>, > > > <0 0>, > > > - <0 300000000>; > > > + <75000000 300000000>; > > > > > > status = "disabled"; > > > }; > > > > Please keep new feature and fixes like this in separate series. This > > could be merged directly in the currently ongoing kernel rc and > > doesn't need to wait for this series. > > > > Or at least keep the commit at the top, so another maintainer can > > simply pick it. > > > > That's what I did. This patch and previous patch are the fixes patches, so they > are posted on top of other dts patches to be merged separately if required. > I agree with Viresh, this is patch 4 in a series where 1-2, 7- are new things. I can pick this from here, but I think it would have been better to send this as 3-4 different series; 1 with DeviceTree fixes, 1 with driver fixes, one that adds interconnect support and one that adds opp support - the latter two with dts changes last... And, the freq-table-hz -> opp transition in dts files must be merged after the driver changes, so this will likely have to wait until 1 release after the driver changes. Regards, Bjorn
On Fri, Jul 21, 2023 at 08:15:36PM -0700, Bjorn Andersson wrote: > On Fri, Jul 21, 2023 at 05:27:31PM +0530, Manivannan Sadhasivam wrote: > > On Fri, Jul 21, 2023 at 12:48:01PM +0530, Viresh Kumar wrote: > > > On 20-07-23, 11:10, Manivannan Sadhasivam wrote: > > > > Minimum frequency of the "ice_core_clk" should be 75MHz as specified in the > > > > downstream vendor devicetree. So fix it! > > > > > > > > https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LA.UM.7.3.r1-09300-sdm845.0/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > > > > > > Fixes: 433f9a57298f ("arm64: dts: sdm845: add Inline Crypto Engine registers and clock") > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > > --- > > > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > > index 9ed74bf72d05..89520a9fe1e3 100644 > > > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > > > @@ -2614,7 +2614,7 @@ ufs_mem_hc: ufshc@1d84000 { > > > > <0 0>, > > > > <0 0>, > > > > <0 0>, > > > > - <0 300000000>; > > > > + <75000000 300000000>; > > > > > > > > status = "disabled"; > > > > }; > > > > > > Please keep new feature and fixes like this in separate series. This > > > could be merged directly in the currently ongoing kernel rc and > > > doesn't need to wait for this series. > > > > > > Or at least keep the commit at the top, so another maintainer can > > > simply pick it. > > > > > > > That's what I did. This patch and previous patch are the fixes patches, so they > > are posted on top of other dts patches to be merged separately if required. > > > > I agree with Viresh, this is patch 4 in a series where 1-2, 7- are new > things. > > I can pick this from here, but I think it would have been better to send > this as 3-4 different series; 1 with DeviceTree fixes, 1 with driver > fixes, one that adds interconnect support and one that adds opp support > - the latter two with dts changes last... > > > And, the freq-table-hz -> opp transition in dts files must be merged > after the driver changes, so this will likely have to wait until 1 > release after the driver changes. > Hmm, Ok. Let me resend the series as you suggested (excluding the patches already merged). - Mani > Regards, > Bjorn
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 9ed74bf72d05..89520a9fe1e3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2614,7 +2614,7 @@ ufs_mem_hc: ufshc@1d84000 { <0 0>, <0 0>, <0 0>, - <0 300000000>; + <75000000 300000000>; status = "disabled"; };
Minimum frequency of the "ice_core_clk" should be 75MHz as specified in the downstream vendor devicetree. So fix it! https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LA.UM.7.3.r1-09300-sdm845.0/arch/arm64/boot/dts/qcom/sdm845.dtsi Fixes: 433f9a57298f ("arm64: dts: sdm845: add Inline Crypto Engine registers and clock") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)