diff mbox series

[v2,1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller

Message ID 20230720135125.21240-2-eric.lin@sifive.com (mailing list archive)
State Changes Requested
Delegated to: Conor Dooley
Headers show
Series Add SiFive Private L2 cache and PMU driver | expand

Checks

Context Check Description
conchuod/cover_letter success Series has a cover letter
conchuod/tree_selection success Guessed tree name to be for-next at HEAD 471aba2e4760
conchuod/fixes_present success Fixes tag not required for -next series
conchuod/maintainers_pattern success MAINTAINERS pattern errors before the patch: 4 and now 4
conchuod/verify_signedoff success Signed-off-by tag matches author and committer
conchuod/kdoc success Errors and warnings before: 0 this patch: 0
conchuod/build_rv64_clang_allmodconfig success Errors and warnings before: 9 this patch: 9
conchuod/module_param success Was 0 now: 0
conchuod/build_rv64_gcc_allmodconfig success Errors and warnings before: 9 this patch: 9
conchuod/build_rv32_defconfig success Build OK
conchuod/dtb_warn_rv64 fail Errors and warnings before: 3 this patch: 73
conchuod/header_inline success No static functions without inline keyword in header files
conchuod/checkpatch warning WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
conchuod/build_rv64_nommu_k210_defconfig success Build OK
conchuod/verify_fixes success No Fixes tag
conchuod/build_rv64_nommu_virt_defconfig success Build OK

Commit Message

Eric Lin July 20, 2023, 1:51 p.m. UTC 
This add YAML DT binding documentation for SiFive Private L2
cache controller

Signed-off-by: Eric Lin <eric.lin@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Nick Hu <nick.hu@sifive.com>
---
 .../bindings/cache/sifive,pl2cache.yaml       | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml

Comments

Rob Herring July 20, 2023, 2:47 p.m. UTC | #1 
On Thu, 20 Jul 2023 21:51:19 +0800, Eric Lin wrote:
> This add YAML DT binding documentation for SiFive Private L2
> cache controller
> 
> Signed-off-by: Eric Lin <eric.lin@sifive.com>
> Reviewed-by: Zong Li <zong.li@sifive.com>
> Reviewed-by: Nick Hu <nick.hu@sifive.com>
> ---
>  .../bindings/cache/sifive,pl2cache.yaml       | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: 'interrupts', 'memory-region' do not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'l3-cache' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'l3-cache' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
	from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230720135125.21240-2-eric.lin@sifive.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
Conor Dooley July 20, 2023, 5:10 p.m. UTC | #2 
Hey Eric,

On Thu, Jul 20, 2023 at 09:51:19PM +0800, Eric Lin wrote:
> This add YAML DT binding documentation for SiFive Private L2
> cache controller
> 
> Signed-off-by: Eric Lin <eric.lin@sifive.com>
> Reviewed-by: Zong Li <zong.li@sifive.com>
> Reviewed-by: Nick Hu <nick.hu@sifive.com>
> ---
>  .../bindings/cache/sifive,pl2cache.yaml       | 62 +++++++++++++++++++

btw, your $subject should be "dt-bindings: cache: ...." rather than
"riscv: sifive".

>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> 
> diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> new file mode 100644
> index 000000000000..ee8356c5eeee
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2023 SiFive, Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SiFive Private L2 Cache Controller
> +
> +maintainers:
> +  - Greentime Hu  <greentime.hu@sifive.com>
> +  - Eric Lin  <eric.lin@sifive.com>

There's extra spaces in these lines for some reason.

> +
> +description:
> +  The SiFive Private L2 Cache Controller is per core and
> +  communicates with both the upstream L1 caches and
> +  downstream L3 cache or memory, enabling a high-performance
> +  cache subsystem.
> +
> +allOf:
> +  - $ref: /schemas/cache-controller.yaml#
> +

I'm pretty sure that I pointed out last time around that you need to add
something like in the ccache driver:

select:
  properties:
    compatible:
      contains:
        enum:
          - sifive,ccache0
          - sifive,fu540-c000-ccache
          - sifive,fu740-c000-ccache

otherwise this binding will be used for anything containing "cache" in
the dt-binding.
For this binding, I think that the following is sufficient:

select:
  properties:
    compatible:
      contains:
          const: sifive,pl2cache1

> +properties:
> +  compatible:
> +    items:
> +      - const: sifive,pl2cache1
> +      - const: cache

You omitted the pl2cache0 from here, that needs to come back! You'll end
up with 2 items entries.
Either way, I can't take this binding without a soc-specific compatible,
per sifive-blocks-ip-versioning.txt..

Thanks,
Conor.
Krzysztof Kozlowski July 21, 2023, 8:34 a.m. UTC | #3 
On 20/07/2023 15:51, Eric Lin wrote:
> This add YAML DT binding documentation for SiFive Private L2
> cache controller
> 
> Signed-off-by: Eric Lin <eric.lin@sifive.com>
> Reviewed-by: Zong Li <zong.li@sifive.com>
> Reviewed-by: Nick Hu <nick.hu@sifive.com>


...

> +properties:
> +  compatible:
> +    items:
> +      - const: sifive,pl2cache1

I still have doubts that it is not used in any SoC. This is what you
said last time: "is not part of any SoC."
If not part of any SoC, then where is it? Why are you adding it to the
kernel?



> +      - const: cache
> +
> +  cache-block-size: true
> +  cache-level: true
> +  cache-sets: true
> +  cache-size: true
> +  cache-unified: true
> +
> +  reg:
> +    maxItems: 1
> +
> +  next-level-cache: true
> +
> +required:
> +  - compatible
> +  - cache-block-size
> +  - cache-level
> +  - cache-sets
> +  - cache-size
> +  - cache-unified
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    cache-controller@10104000 {
> +        compatible = "sifive,pl2cache1","cache";

Missing space.

> +        cache-block-size = <64>;
> +        cache-level = <2>;
> +        cache-sets = <512>;
> +        cache-size = <262144>;
> +        cache-unified;
> +        reg = <0x10104000 0x4000>;

reg is after compatible.

> +        next-level-cache = <&L4>;
> +    };

Best regards,
Krzysztof
Eric Lin July 21, 2023, 10:21 a.m. UTC | #4 
Hi Rob,

On Thu, Jul 20, 2023 at 10:47 PM Rob Herring <robh@kernel.org> wrote:
>
>
> On Thu, 20 Jul 2023 21:51:19 +0800, Eric Lin wrote:
> > This add YAML DT binding documentation for SiFive Private L2
> > cache controller
> >
> > Signed-off-by: Eric Lin <eric.lin@sifive.com>
> > Reviewed-by: Zong Li <zong.li@sifive.com>
> > Reviewed-by: Nick Hu <nick.hu@sifive.com>
> > ---
> >  .../bindings/cache/sifive,pl2cache.yaml       | 62 +++++++++++++++++++
> >  1 file changed, 62 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: 'interrupts', 'memory-region' do not match any of the regexes: 'pinctrl-[0-9]+'
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'l3-cache' does not match any of the regexes: 'pinctrl-[0-9]+'
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'l3-cache' does not match any of the regexes: 'pinctrl-[0-9]+'
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
>         from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230720135125.21240-2-eric.lin@sifive.com
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
>

Sorry for the errors. I forgot to run `make dt_binding_check`.
I'll fix it in the next version. Thanks for the review.

Best regards,
Eric Lin
Eric Lin July 28, 2023, 6:01 a.m. UTC | #5 
Hi Krzysztof,

On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 20/07/2023 15:51, Eric Lin wrote:
> > This add YAML DT binding documentation for SiFive Private L2
> > cache controller
> >
> > Signed-off-by: Eric Lin <eric.lin@sifive.com>
> > Reviewed-by: Zong Li <zong.li@sifive.com>
> > Reviewed-by: Nick Hu <nick.hu@sifive.com>
>
>
> ...
>
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: sifive,pl2cache1
>
> I still have doubts that it is not used in any SoC. This is what you
> said last time: "is not part of any SoC."
> If not part of any SoC, then where is it? Why are you adding it to the
> kernel?
>

Sorry for the late reply. I didn't describe it clearly last time.
Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
The pl2cache0 is used in unmatched board SoC. The pl2cache1 is
utilized in our internal FPGA platform for evaluation; it's our core
IP.

>
>
> > +      - const: cache
> > +
> > +  cache-block-size: true
> > +  cache-level: true
> > +  cache-sets: true
> > +  cache-size: true
> > +  cache-unified: true
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  next-level-cache: true
> > +
> > +required:
> > +  - compatible
> > +  - cache-block-size
> > +  - cache-level
> > +  - cache-sets
> > +  - cache-size
> > +  - cache-unified
> > +  - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    cache-controller@10104000 {
> > +        compatible = "sifive,pl2cache1","cache";
>
> Missing space.

OK, I'll fix it in the next version.

>
> > +        cache-block-size = <64>;
> > +        cache-level = <2>;
> > +        cache-sets = <512>;
> > +        cache-size = <262144>;
> > +        cache-unified;
> > +        reg = <0x10104000 0x4000>;
>
> reg is after compatible.

OK, I'll fix it in the next version.
Thanks for your review.

Best regards,
Eric Lin

>
> > +        next-level-cache = <&L4>;
> > +    };
>
> Best regards,
> Krzysztof
>
Conor Dooley July 28, 2023, 6:46 a.m. UTC | #6 
On Fri, Jul 28, 2023 at 02:01:28PM +0800, Eric Lin wrote:
> Hi Krzysztof,
> 
> On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> >
> > On 20/07/2023 15:51, Eric Lin wrote:
> > > This add YAML DT binding documentation for SiFive Private L2
> > > cache controller
> > >
> > > Signed-off-by: Eric Lin <eric.lin@sifive.com>
> > > Reviewed-by: Zong Li <zong.li@sifive.com>
> > > Reviewed-by: Nick Hu <nick.hu@sifive.com>
> >
> >
> > ...
> >
> > > +properties:
> > > +  compatible:
> > > +    items:
> > > +      - const: sifive,pl2cache1
> >
> > I still have doubts that it is not used in any SoC. This is what you
> > said last time: "is not part of any SoC."
> > If not part of any SoC, then where is it? Why are you adding it to the
> > kernel?
> >
> 
> Sorry for the late reply. I didn't describe it clearly last time.
> Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
> The pl2cache0 is used in unmatched board SoC.

Wait a second, does the fu740 on the unmatched not have a ccache as
it's L2 cache?

> The pl2cache1 is
> utilized in our internal FPGA platform for evaluation; it's our core
> IP.
Krzysztof Kozlowski July 28, 2023, 6:58 a.m. UTC | #7 
On 28/07/2023 08:01, Eric Lin wrote:
> Hi Krzysztof,
> 
> On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 20/07/2023 15:51, Eric Lin wrote:
>>> This add YAML DT binding documentation for SiFive Private L2
>>> cache controller
>>>
>>> Signed-off-by: Eric Lin <eric.lin@sifive.com>
>>> Reviewed-by: Zong Li <zong.li@sifive.com>
>>> Reviewed-by: Nick Hu <nick.hu@sifive.com>
>>
>>
>> ...
>>
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - const: sifive,pl2cache1
>>
>> I still have doubts that it is not used in any SoC. This is what you
>> said last time: "is not part of any SoC."
>> If not part of any SoC, then where is it? Why are you adding it to the
>> kernel?
>>
> 
> Sorry for the late reply. I didn't describe it clearly last time.
> Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
> The pl2cache0 is used in unmatched board SoC. The pl2cache1 is
> utilized in our internal FPGA platform for evaluation; it's our core
> IP.

And why do you add bindings for some internal FPGA IP block which does
not interface with any SW?

Best regards,
Krzysztof
Conor Dooley July 28, 2023, 7:05 a.m. UTC | #8 
On Thu, Jul 20, 2023 at 06:10:51PM +0100, Conor Dooley wrote:
> Hey Eric,
> 
> On Thu, Jul 20, 2023 at 09:51:19PM +0800, Eric Lin wrote:
> > This add YAML DT binding documentation for SiFive Private L2
> > cache controller
> > 
> > Signed-off-by: Eric Lin <eric.lin@sifive.com>
> > Reviewed-by: Zong Li <zong.li@sifive.com>
> > Reviewed-by: Nick Hu <nick.hu@sifive.com>
> > ---
> >  .../bindings/cache/sifive,pl2cache.yaml       | 62 +++++++++++++++++++
> 
> btw, your $subject should be "dt-bindings: cache: ...." rather than
> "riscv: sifive".
> 
> >  1 file changed, 62 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > new file mode 100644
> > index 000000000000..ee8356c5eeee
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > @@ -0,0 +1,62 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright (C) 2023 SiFive, Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SiFive Private L2 Cache Controller
> > +
> > +maintainers:
> > +  - Greentime Hu  <greentime.hu@sifive.com>
> > +  - Eric Lin  <eric.lin@sifive.com>
> 
> There's extra spaces in these lines for some reason.
> 
> > +
> > +description:
> > +  The SiFive Private L2 Cache Controller is per core and
> > +  communicates with both the upstream L1 caches and
> > +  downstream L3 cache or memory, enabling a high-performance
> > +  cache subsystem.
> > +
> > +allOf:
> > +  - $ref: /schemas/cache-controller.yaml#
> > +
> 
> I'm pretty sure that I pointed out last time around that you need to add
> something like in the ccache driver:
> 
> select:
>   properties:
>     compatible:
>       contains:
>         enum:
>           - sifive,ccache0
>           - sifive,fu540-c000-ccache
>           - sifive,fu740-c000-ccache
> 
> otherwise this binding will be used for anything containing "cache" in
> the dt-binding.
> For this binding, I think that the following is sufficient:
> 
> select:
>   properties:
>     compatible:
>       contains:
>           const: sifive,pl2cache1
> 
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: sifive,pl2cache1
> > +      - const: cache
> 
> You omitted the pl2cache0 from here, that needs to come back! You'll end
> up with 2 items entries.
> Either way, I can't take this binding without a soc-specific compatible,
> per sifive-blocks-ip-versioning.txt..

Further, "sifive,perfmon-counters" is an undocumented property.

Thanks,
Conor.
Eric Lin July 28, 2023, 7:20 a.m. UTC | #9 
On Fri, Jul 28, 2023 at 2:47 PM Conor Dooley <conor.dooley@microchip.com> wrote:
>
> On Fri, Jul 28, 2023 at 02:01:28PM +0800, Eric Lin wrote:
> > Hi Krzysztof,
> >
> > On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> > >
> > > On 20/07/2023 15:51, Eric Lin wrote:
> > > > This add YAML DT binding documentation for SiFive Private L2
> > > > cache controller
> > > >
> > > > Signed-off-by: Eric Lin <eric.lin@sifive.com>
> > > > Reviewed-by: Zong Li <zong.li@sifive.com>
> > > > Reviewed-by: Nick Hu <nick.hu@sifive.com>
> > >
> > >
> > > ...
> > >
> > > > +properties:
> > > > +  compatible:
> > > > +    items:
> > > > +      - const: sifive,pl2cache1
> > >
> > > I still have doubts that it is not used in any SoC. This is what you
> > > said last time: "is not part of any SoC."
> > > If not part of any SoC, then where is it? Why are you adding it to the
> > > kernel?
> > >
> >
> > Sorry for the late reply. I didn't describe it clearly last time.
> > Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
> > The pl2cache0 is used in unmatched board SoC.
>
> Wait a second, does the fu740 on the unmatched not have a ccache as
> it's L2 cache?
>

Hi Conor,
Sorry, I misremember the L2 cache on the unmatched board.
I just check again. The unmatched board L2 cache is ccache not
pl2cache0. You are right. Thanks.

Best regards,
Eric Lin

> > The pl2cache1 is
> > utilized in our internal FPGA platform for evaluation; it's our core
> > IP.
Eric Lin July 28, 2023, 8:24 a.m. UTC | #10 
Hi Conor,

On Fri, Jul 28, 2023 at 3:06 PM Conor Dooley <conor.dooley@microchip.com> wrote:
>
> On Thu, Jul 20, 2023 at 06:10:51PM +0100, Conor Dooley wrote:
> > Hey Eric,
> >
> > On Thu, Jul 20, 2023 at 09:51:19PM +0800, Eric Lin wrote:
> > > This add YAML DT binding documentation for SiFive Private L2
> > > cache controller
> > >
> > > Signed-off-by: Eric Lin <eric.lin@sifive.com>
> > > Reviewed-by: Zong Li <zong.li@sifive.com>
> > > Reviewed-by: Nick Hu <nick.hu@sifive.com>
> > > ---
> > >  .../bindings/cache/sifive,pl2cache.yaml       | 62 +++++++++++++++++++
> >
> > btw, your $subject should be "dt-bindings: cache: ...." rather than
> > "riscv: sifive".
> >

OK, I'll fix it in v3.

> > >  1 file changed, 62 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > > new file mode 100644
> > > index 000000000000..ee8356c5eeee
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > > @@ -0,0 +1,62 @@
> > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > +# Copyright (C) 2023 SiFive, Inc.
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: SiFive Private L2 Cache Controller
> > > +
> > > +maintainers:
> > > +  - Greentime Hu  <greentime.hu@sifive.com>
> > > +  - Eric Lin  <eric.lin@sifive.com>
> >
> > There's extra spaces in these lines for some reason.
> >

OK, I'll fix it in v3.

> > > +
> > > +description:
> > > +  The SiFive Private L2 Cache Controller is per core and
> > > +  communicates with both the upstream L1 caches and
> > > +  downstream L3 cache or memory, enabling a high-performance
> > > +  cache subsystem.
> > > +
> > > +allOf:
> > > +  - $ref: /schemas/cache-controller.yaml#
> > > +
> >
> > I'm pretty sure that I pointed out last time around that you need to add
> > something like in the ccache driver:
> >
> > select:
> >   properties:
> >     compatible:
> >       contains:
> >         enum:
> >           - sifive,ccache0
> >           - sifive,fu540-c000-ccache
> >           - sifive,fu740-c000-ccache
> >
> > otherwise this binding will be used for anything containing "cache" in
> > the dt-binding.
> > For this binding, I think that the following is sufficient:
> >
> > select:
> >   properties:
> >     compatible:
> >       contains:
> >           const: sifive,pl2cache1
> >

Sorry, I misunderstood your meaning.
To be honest, I'm not quite familiar with the usage of the select property.
When should we use the select property?
May I ask, is there a document to detail introduce each property and
its usage like the device-tree spec?
I think it would be very helpful for beginners writing correct
dt-binding and it can save much reviewers time.
Thanks for your kind explanation, I'll fix it in v3.

> > > +properties:
> > > +  compatible:
> > > +    items:
> > > +      - const: sifive,pl2cache1
> > > +      - const: cache
> >
> > You omitted the pl2cache0 from here, that needs to come back! You'll end
> > up with 2 items entries.

OK, it should be as follows, right?

+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: sifive,pl2cache0
+          - const: sifive,pl2cache1
+          - const: cache
+      - items:
+          - const: sifive,pl2cache1
+          - const: cache

I'll fix it in v3. Thanks.

> > Either way, I can't take this binding without a soc-specific compatible,
> > per sifive-blocks-ip-versioning.txt..
>
> Further, "sifive,perfmon-counters" is an undocumented property.
>

OK, I'll add "sifive,perfmon-counters" property in v3.
Thanks for your kind review.

Best regards,
Eric Lin

> Thanks,
> Conor.
Eric Lin July 28, 2023, 9:04 a.m. UTC | #11 
On Fri, Jul 28, 2023 at 2:58 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 28/07/2023 08:01, Eric Lin wrote:
> > Hi Krzysztof,
> >
> > On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 20/07/2023 15:51, Eric Lin wrote:
> >>> This add YAML DT binding documentation for SiFive Private L2
> >>> cache controller
> >>>
> >>> Signed-off-by: Eric Lin <eric.lin@sifive.com>
> >>> Reviewed-by: Zong Li <zong.li@sifive.com>
> >>> Reviewed-by: Nick Hu <nick.hu@sifive.com>
> >>
> >>
> >> ...
> >>
> >>> +properties:
> >>> +  compatible:
> >>> +    items:
> >>> +      - const: sifive,pl2cache1
> >>
> >> I still have doubts that it is not used in any SoC. This is what you
> >> said last time: "is not part of any SoC."
> >> If not part of any SoC, then where is it? Why are you adding it to the
> >> kernel?
> >>
> >
> > Sorry for the late reply. I didn't describe it clearly last time.
> > Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
> > The pl2cache0 is used in unmatched board SoC. The pl2cache1 is
> > utilized in our internal FPGA platform for evaluation; it's our core
> > IP.
>
> And why do you add bindings for some internal FPGA IP block which does
> not interface with any SW?
>

Hi Krzysztof,
The pl2cache has mmio interface for SW. Thanks.

Best regards,
Eric Lin

> Best regards,
> Krzysztof
>
Krzysztof Kozlowski July 28, 2023, 9:39 a.m. UTC | #12 
On 28/07/2023 11:04, Eric Lin wrote:
> On Fri, Jul 28, 2023 at 2:58 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 28/07/2023 08:01, Eric Lin wrote:
>>> Hi Krzysztof,
>>>
>>> On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 20/07/2023 15:51, Eric Lin wrote:
>>>>> This add YAML DT binding documentation for SiFive Private L2
>>>>> cache controller
>>>>>
>>>>> Signed-off-by: Eric Lin <eric.lin@sifive.com>
>>>>> Reviewed-by: Zong Li <zong.li@sifive.com>
>>>>> Reviewed-by: Nick Hu <nick.hu@sifive.com>
>>>>
>>>>
>>>> ...
>>>>
>>>>> +properties:
>>>>> +  compatible:
>>>>> +    items:
>>>>> +      - const: sifive,pl2cache1
>>>>
>>>> I still have doubts that it is not used in any SoC. This is what you
>>>> said last time: "is not part of any SoC."
>>>> If not part of any SoC, then where is it? Why are you adding it to the
>>>> kernel?
>>>>
>>>
>>> Sorry for the late reply. I didn't describe it clearly last time.
>>> Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
>>> The pl2cache0 is used in unmatched board SoC. The pl2cache1 is
>>> utilized in our internal FPGA platform for evaluation; it's our core
>>> IP.
>>
>> And why do you add bindings for some internal FPGA IP block which does
>> not interface with any SW?
>>
> 
> Hi Krzysztof,
> The pl2cache has mmio interface for SW. Thanks.

Then did you mean that FPGA represented some model of your SoC? If so,
what are other bindings for that FPGA components?

Best regards,
Krzysztof
Conor Dooley July 28, 2023, 11:06 a.m. UTC | #13 
On Fri, Jul 28, 2023 at 04:24:08PM +0800, Eric Lin wrote:
> On Fri, Jul 28, 2023 at 3:06 PM Conor Dooley <conor.dooley@microchip.com> wrote:
> > On Thu, Jul 20, 2023 at 06:10:51PM +0100, Conor Dooley wrote:
> > > On Thu, Jul 20, 2023 at 09:51:19PM +0800, Eric Lin wrote:

> > > > +description:
> > > > +  The SiFive Private L2 Cache Controller is per core and
> > > > +  communicates with both the upstream L1 caches and
> > > > +  downstream L3 cache or memory, enabling a high-performance
> > > > +  cache subsystem.
> > > > +
> > > > +allOf:
> > > > +  - $ref: /schemas/cache-controller.yaml#
> > > > +
> > >
> > > I'm pretty sure that I pointed out last time around that you need to add
> > > something like in the ccache driver:
> > >
> > > select:
> > >   properties:
> > >     compatible:
> > >       contains:
> > >         enum:
> > >           - sifive,ccache0
> > >           - sifive,fu540-c000-ccache
> > >           - sifive,fu740-c000-ccache
> > >
> > > otherwise this binding will be used for anything containing "cache" in
> > > the dt-binding.
> > > For this binding, I think that the following is sufficient:
> > >
> > > select:
> > >   properties:
> > >     compatible:
> > >       contains:
> > >           const: sifive,pl2cache1
> > >
> 
> Sorry, I misunderstood your meaning.
> To be honest, I'm not quite familiar with the usage of the select property.
> When should we use the select property?
> May I ask, is there a document to detail introduce each property and
> its usage like the device-tree spec?
> I think it would be very helpful for beginners writing correct
> dt-binding and it can save much reviewers time.

You need this select because otherwise this binding will match against
every other user of "cache" in the tree. It's explained here:
https://docs.kernel.org/devicetree/bindings/writing-schema.html

Thanks,
Conor.
Eric Lin Aug. 1, 2023, 10:59 a.m. UTC | #14 
On Fri, Jul 28, 2023 at 5:39 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 28/07/2023 11:04, Eric Lin wrote:
> > On Fri, Jul 28, 2023 at 2:58 PM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 28/07/2023 08:01, Eric Lin wrote:
> >>> Hi Krzysztof,
> >>>
> >>> On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 20/07/2023 15:51, Eric Lin wrote:
> >>>>> This add YAML DT binding documentation for SiFive Private L2
> >>>>> cache controller
> >>>>>
> >>>>> Signed-off-by: Eric Lin <eric.lin@sifive.com>
> >>>>> Reviewed-by: Zong Li <zong.li@sifive.com>
> >>>>> Reviewed-by: Nick Hu <nick.hu@sifive.com>
> >>>>
> >>>>
> >>>> ...
> >>>>
> >>>>> +properties:
> >>>>> +  compatible:
> >>>>> +    items:
> >>>>> +      - const: sifive,pl2cache1
> >>>>
> >>>> I still have doubts that it is not used in any SoC. This is what you
> >>>> said last time: "is not part of any SoC."
> >>>> If not part of any SoC, then where is it? Why are you adding it to the
> >>>> kernel?
> >>>>
> >>>
> >>> Sorry for the late reply. I didn't describe it clearly last time.
> >>> Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
> >>> The pl2cache0 is used in unmatched board SoC. The pl2cache1 is
> >>> utilized in our internal FPGA platform for evaluation; it's our core
> >>> IP.
> >>
> >> And why do you add bindings for some internal FPGA IP block which does
> >> not interface with any SW?
> >>
> >
> > Hi Krzysztof,
> > The pl2cache has mmio interface for SW. Thanks.
>
> Then did you mean that FPGA represented some model of your SoC? If so,
> what are other bindings for that FPGA components?
>
Hi Krzysztof,

Sorry for the late reply.
Yes, here are the devices dt-binding that we use on the internal FPGA
SoC platform. Thanks.

uart:
Documentation/devicetree/bindings/serial/sifive-serial.yaml

gpio:
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml

dma:
Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml

spi:
Documentation/devicetree/bindings/spi/spi-sifive.yaml

Best regards,
Eric Lin

> Best regards,
> Krzysztof
>
Eric Lin Sept. 5, 2023, 3:07 p.m. UTC | #15 
Hi Conor and Krzysztof,

On Fri, Jul 21, 2023 at 1:10 AM Conor Dooley <conor@kernel.org> wrote:
>
> Hey Eric,
>
> On Thu, Jul 20, 2023 at 09:51:19PM +0800, Eric Lin wrote:
> > This add YAML DT binding documentation for SiFive Private L2
> > cache controller
> >
> > Signed-off-by: Eric Lin <eric.lin@sifive.com>
> > Reviewed-by: Zong Li <zong.li@sifive.com>
> > Reviewed-by: Nick Hu <nick.hu@sifive.com>
> > ---
> >  .../bindings/cache/sifive,pl2cache.yaml       | 62 +++++++++++++++++++
>
> btw, your $subject should be "dt-bindings: cache: ...." rather than
> "riscv: sifive".
>
> >  1 file changed, 62 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > new file mode 100644
> > index 000000000000..ee8356c5eeee
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > @@ -0,0 +1,62 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright (C) 2023 SiFive, Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SiFive Private L2 Cache Controller
> > +
> > +maintainers:
> > +  - Greentime Hu  <greentime.hu@sifive.com>
> > +  - Eric Lin  <eric.lin@sifive.com>
>
> There's extra spaces in these lines for some reason.
>
> > +
> > +description:
> > +  The SiFive Private L2 Cache Controller is per core and
> > +  communicates with both the upstream L1 caches and
> > +  downstream L3 cache or memory, enabling a high-performance
> > +  cache subsystem.
> > +
> > +allOf:
> > +  - $ref: /schemas/cache-controller.yaml#
> > +
>
> I'm pretty sure that I pointed out last time around that you need to add
> something like in the ccache driver:
>
> select:
>   properties:
>     compatible:
>       contains:
>         enum:
>           - sifive,ccache0
>           - sifive,fu540-c000-ccache
>           - sifive,fu740-c000-ccache
>
> otherwise this binding will be used for anything containing "cache" in
> the dt-binding.
> For this binding, I think that the following is sufficient:
>
> select:
>   properties:
>     compatible:
>       contains:
>           const: sifive,pl2cache1
>
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: sifive,pl2cache1
> > +      - const: cache
>
> You omitted the pl2cache0 from here, that needs to come back! You'll end
> up with 2 items entries.
> Either way, I can't take this binding without a soc-specific compatible,
> per sifive-blocks-ip-versioning.txt..
>
Sorry for the late reply.
OK, I will wait until the customer's SoC tape-out before upstreaming
the PL2 cache and PMU drivers.
Thank you for your review.

Best regards,
Eric Lin

> Thanks,
> Conor.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
new file mode 100644
index 000000000000..ee8356c5eeee
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
@@ -0,0 +1,62 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2023 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive Private L2 Cache Controller
+
+maintainers:
+  - Greentime Hu  <greentime.hu@sifive.com>
+  - Eric Lin  <eric.lin@sifive.com>
+
+description:
+  The SiFive Private L2 Cache Controller is per core and
+  communicates with both the upstream L1 caches and
+  downstream L3 cache or memory, enabling a high-performance
+  cache subsystem.
+
+allOf:
+  - $ref: /schemas/cache-controller.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: sifive,pl2cache1
+      - const: cache
+
+  cache-block-size: true
+  cache-level: true
+  cache-sets: true
+  cache-size: true
+  cache-unified: true
+
+  reg:
+    maxItems: 1
+
+  next-level-cache: true
+
+required:
+  - compatible
+  - cache-block-size
+  - cache-level
+  - cache-sets
+  - cache-size
+  - cache-unified
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    cache-controller@10104000 {
+        compatible = "sifive,pl2cache1","cache";
+        cache-block-size = <64>;
+        cache-level = <2>;
+        cache-sets = <512>;
+        cache-size = <262144>;
+        cache-unified;
+        reg = <0x10104000 0x4000>;
+        next-level-cache = <&L4>;
+    };