[v1,3/3] perf arm-spe: Support data source for Cortex-X4 CPU

Commit Message

Leo Yan July 17, 2023, 5:43 a.m. UTC

We have a CPU list to maintain Neoverse CPUs (N1/N2/V2), this list is
used for parsing data source packet.  Since Cortex-x4 CPU shares the
same data source format with Neoverse CPUs, this commit adds Cortex-x4
CPU into the CPU list so we can reuse the parsing logic.

The CPU list was assumed for only Neoverse CPUs, but now Cortex-X4 has
been added into the list.  To avoid Neoverse specific naming, this patch
renames the variables and function as the default data source format.

Signed-off-by: Leo Yan <[e-mail]>
---
 tools/perf/util/arm-spe.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

Comments

Will Deacon July 28, 2023, 2:22 p.m. UTC | #1

On Mon, Jul 24, 2023 at 07:05:09PM +0800, Leo Yan wrote:
> On Mon, Jul 24, 2023 at 12:27:31PM +0530, Anshuman Khandual wrote:
> 
> [...]
> 
> > > -static const struct midr_range neoverse_spe[] = {
> > > +static const struct midr_range cpus_use_default_data_src[] = {
> > 
> > Is not 'cpus_use_default_data_src' too long ? 'use' could be dropped ?
> 
> Okay, I can drop 'use'.
> 
> > >  	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
> > >  	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> > >  	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
> > > +	MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
> > >  	{},
> > >  };
> 
> [...]
> 
> > >  static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr)
> > >  {
> > >  	union perf_mem_data_src	data_src = { .mem_op = PERF_MEM_OP_NA };
> > > -	bool is_neoverse = is_midr_in_range_list(midr, neoverse_spe);
> > > +	bool is_default_dc =
> > 
> > _dc stands for ?
> 
> Thanks for pointing out this; actually I mean '_ds' which stands for
> data source.  Will spin a new patch for this.

Thanks. Please can you put patch 2 (the one touching tools) at the end of
the series, too? That way I can easily pick up the kernel changes.

Will

Patch

diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index afbd5869f6bf..c2cdb9f2e188 100644
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -409,15 +409,16 @@  static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq,
 	return arm_spe_deliver_synth_event(spe, speq, event, &sample);
 }
 
-static const struct midr_range neoverse_spe[] = {
+static const struct midr_range cpus_use_default_data_src[] = {
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
+	MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
 	{},
 };
 
-static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *record,
-						union perf_mem_data_src *data_src)
+static void arm_spe__synth_data_source_default(const struct arm_spe_record *record,
+					       union perf_mem_data_src *data_src)
 {
 	/*
 	 * Even though four levels of cache hierarchy are possible, no known
@@ -518,7 +519,8 @@  static void arm_spe__synth_data_source_generic(const struct arm_spe_record *reco
 static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr)
 {
 	union perf_mem_data_src	data_src = { .mem_op = PERF_MEM_OP_NA };
-	bool is_neoverse = is_midr_in_range_list(midr, neoverse_spe);
+	bool is_default_dc =
+		is_midr_in_range_list(midr, cpus_use_default_data_src);
 
 	if (record->op & ARM_SPE_OP_LD)
 		data_src.mem_op = PERF_MEM_OP_LOAD;
@@ -527,8 +529,8 @@  static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 m
 	else
 		return 0;
 
-	if (is_neoverse)
-		arm_spe__synth_data_source_neoverse(record, &data_src);
+	if (is_default_dc)
+		arm_spe__synth_data_source_default(record, &data_src);
 	else
 		arm_spe__synth_data_source_generic(record, &data_src);