diff mbox series

[1/4] xen/ppc: Switch to medium PIC code model

Message ID c72c242988295b665a8bd235a351806dc112ad01.1690934409.git.sanastasio@raptorengineering.com (mailing list archive)
State New, archived
Headers show
Series xen/ppc: Add PowerNV bare metal support | expand

Commit Message

Shawn Anastasio Aug. 2, 2023, 12:11 a.m. UTC 
Switch Xen to the medium PIC code model on Power. Among other things,
this allows us to be load address agnostic and will open the door to
booting on bare metal PowerNV systems that don't use OpenFirmware.

Also update XEN_VIRT_START to 0xc000000000000000, which is equivalent to
address 0x0 when the MMU is off. This prevents Open Firmware from
loading Xen at an offset from its base load address, so the DECL_SECTION
hack in xen.lds.S is no longer required.

Signed-off-by: Shawn Anastasio <sanastasio@raptorengineering.com>
---
Changed in v2:
  - Remove stray newline
  - Use label instead of .+4 in TOC setup branch

 xen/arch/ppc/arch.mk                 |  2 +-
 xen/arch/ppc/include/asm/asm-defns.h |  7 +++++
 xen/arch/ppc/include/asm/config.h    |  2 +-
 xen/arch/ppc/ppc64/head.S            | 12 +++++---
 xen/arch/ppc/xen.lds.S               | 44 ++++++++++------------------
 5 files changed, 33 insertions(+), 34 deletions(-)

--
2.30.2

Comments

Jan Beulich Aug. 2, 2023, 7:16 a.m. UTC | #1 
On 02.08.2023 02:11, Shawn Anastasio wrote:
> --- a/xen/arch/ppc/include/asm/asm-defns.h
> +++ b/xen/arch/ppc/include/asm/asm-defns.h
> @@ -16,6 +16,13 @@
>      lis reg, (val) @h;                                                       \
>      ori reg, reg, (val) @l;                                                  \
> 
> +/*
> + * Load the address of a symbol from the TOC into the specified GPR.
> + */
> +#define LOAD_REG_ADDR(reg,name)                                              \
> +    addis reg,%r2,name@toc@ha;                                               \
> +    addi  reg,reg,name@toc@l

Didn't you indicate you'd add blanks after the commas (also) here?

> --- a/xen/arch/ppc/ppc64/head.S
> +++ b/xen/arch/ppc/ppc64/head.S
> @@ -1,6 +1,7 @@
>  /* SPDX-License-Identifier: GPL-2.0-or-later */
> 
>  #include <asm/asm-defns.h>
> +#include <asm/asm-offsets.h>
> 
>      .section .text.header, "ax", %progbits
> 
> @@ -11,16 +12,19 @@ ENTRY(start)
>      FIXUP_ENDIAN
> 
>      /* set up the TOC pointer */
> -    LOAD_IMM32(%r2, .TOC.)
> +    bcl	    20, 31, 1f

Hard tab slipped in.

I'm happy to take care of both while committing; then:
Acked-by: Jan Beulich <jbeulich@suse.com>

Jan
Shawn Anastasio Aug. 7, 2023, 4:22 p.m. UTC | #2 
On 8/2/23 2:16 AM, Jan Beulich wrote:
> On 02.08.2023 02:11, Shawn Anastasio wrote:
>> --- a/xen/arch/ppc/include/asm/asm-defns.h
>> +++ b/xen/arch/ppc/include/asm/asm-defns.h
>> @@ -16,6 +16,13 @@
>>      lis reg, (val) @h;                                                       \
>>      ori reg, reg, (val) @l;                                                  \
>>
>> +/*
>> + * Load the address of a symbol from the TOC into the specified GPR.
>> + */
>> +#define LOAD_REG_ADDR(reg,name)                                              \
>> +    addis reg,%r2,name@toc@ha;                                               \
>> +    addi  reg,reg,name@toc@l
> 
> Didn't you indicate you'd add blanks after the commas (also) here?
> 
>> --- a/xen/arch/ppc/ppc64/head.S
>> +++ b/xen/arch/ppc/ppc64/head.S
>> @@ -1,6 +1,7 @@
>>  /* SPDX-License-Identifier: GPL-2.0-or-later */
>>
>>  #include <asm/asm-defns.h>
>> +#include <asm/asm-offsets.h>
>>
>>      .section .text.header, "ax", %progbits
>>
>> @@ -11,16 +12,19 @@ ENTRY(start)
>>      FIXUP_ENDIAN
>>
>>      /* set up the TOC pointer */
>> -    LOAD_IMM32(%r2, .TOC.)
>> +    bcl	    20, 31, 1f
> 
> Hard tab slipped in.
> 
> I'm happy to take care of both while committing; then:
> Acked-by: Jan Beulich <jbeulich@suse.com>

Thanks, Jan. Just to clarify, are there any outstanding comments that I
need to address in this series, or are they all able to be handled by
you during commit?

> Jan

- Shawn
Jan Beulich Aug. 8, 2023, 5:59 a.m. UTC | #3 
On 07.08.2023 18:22, Shawn Anastasio wrote:
> On 8/2/23 2:16 AM, Jan Beulich wrote:
>> On 02.08.2023 02:11, Shawn Anastasio wrote:
>>> --- a/xen/arch/ppc/include/asm/asm-defns.h
>>> +++ b/xen/arch/ppc/include/asm/asm-defns.h
>>> @@ -16,6 +16,13 @@
>>>      lis reg, (val) @h;                                                       \
>>>      ori reg, reg, (val) @l;                                                  \
>>>
>>> +/*
>>> + * Load the address of a symbol from the TOC into the specified GPR.
>>> + */
>>> +#define LOAD_REG_ADDR(reg,name)                                              \
>>> +    addis reg,%r2,name@toc@ha;                                               \
>>> +    addi  reg,reg,name@toc@l
>>
>> Didn't you indicate you'd add blanks after the commas (also) here?
>>
>>> --- a/xen/arch/ppc/ppc64/head.S
>>> +++ b/xen/arch/ppc/ppc64/head.S
>>> @@ -1,6 +1,7 @@
>>>  /* SPDX-License-Identifier: GPL-2.0-or-later */
>>>
>>>  #include <asm/asm-defns.h>
>>> +#include <asm/asm-offsets.h>
>>>
>>>      .section .text.header, "ax", %progbits
>>>
>>> @@ -11,16 +12,19 @@ ENTRY(start)
>>>      FIXUP_ENDIAN
>>>
>>>      /* set up the TOC pointer */
>>> -    LOAD_IMM32(%r2, .TOC.)
>>> +    bcl	    20, 31, 1f
>>
>> Hard tab slipped in.
>>
>> I'm happy to take care of both while committing; then:
>> Acked-by: Jan Beulich <jbeulich@suse.com>
> 
> Thanks, Jan. Just to clarify, are there any outstanding comments that I
> need to address in this series, or are they all able to be handled by
> you during commit?

I intend to take care of the minor changes to the last two patches
during commit. The patch here has gone in already anyway.

Jan
diff mbox series

Patch

diff --git a/xen/arch/ppc/arch.mk b/xen/arch/ppc/arch.mk
index 7eec22c283..0183b9ac6a 100644
--- a/xen/arch/ppc/arch.mk
+++ b/xen/arch/ppc/arch.mk
@@ -5,7 +5,7 @@  ppc-march-$(CONFIG_POWER_ISA_2_07B) := power8
 ppc-march-$(CONFIG_POWER_ISA_3_00) := power9

 CFLAGS += -m64 -mlittle-endian -mcpu=$(ppc-march-y)
-CFLAGS += -mstrict-align -mcmodel=large -mabi=elfv2 -mno-altivec -mno-vsx
+CFLAGS += -mstrict-align -mcmodel=medium -mabi=elfv2 -fPIC -mno-altivec -mno-vsx -msoft-float

 LDFLAGS += -m elf64lppc

diff --git a/xen/arch/ppc/include/asm/asm-defns.h b/xen/arch/ppc/include/asm/asm-defns.h
index 35b1c89d4e..5821f9024d 100644
--- a/xen/arch/ppc/include/asm/asm-defns.h
+++ b/xen/arch/ppc/include/asm/asm-defns.h
@@ -16,6 +16,13 @@ 
     lis reg, (val) @h;                                                       \
     ori reg, reg, (val) @l;                                                  \

+/*
+ * Load the address of a symbol from the TOC into the specified GPR.
+ */
+#define LOAD_REG_ADDR(reg,name)                                              \
+    addis reg,%r2,name@toc@ha;                                               \
+    addi  reg,reg,name@toc@l
+
 /*
  * Depending on how we were booted, the CPU could be running in either
  * Little Endian or Big Endian mode. The following trampoline from Linux
diff --git a/xen/arch/ppc/include/asm/config.h b/xen/arch/ppc/include/asm/config.h
index cb27d2781e..d060f0dca7 100644
--- a/xen/arch/ppc/include/asm/config.h
+++ b/xen/arch/ppc/include/asm/config.h
@@ -39,7 +39,7 @@ 
     name:
 #endif

-#define XEN_VIRT_START _AT(UL, 0x400000)
+#define XEN_VIRT_START _AT(UL, 0xc000000000000000)

 #define SMP_CACHE_BYTES (1 << 6)

diff --git a/xen/arch/ppc/ppc64/head.S b/xen/arch/ppc/ppc64/head.S
index 02ff520458..4172f1b8ec 100644
--- a/xen/arch/ppc/ppc64/head.S
+++ b/xen/arch/ppc/ppc64/head.S
@@ -1,6 +1,7 @@ 
 /* SPDX-License-Identifier: GPL-2.0-or-later */

 #include <asm/asm-defns.h>
+#include <asm/asm-offsets.h>

     .section .text.header, "ax", %progbits

@@ -11,16 +12,19 @@  ENTRY(start)
     FIXUP_ENDIAN

     /* set up the TOC pointer */
-    LOAD_IMM32(%r2, .TOC.)
+    bcl	    20, 31, 1f
+1:  mflr    %r12
+    addis   %r2, %r12, .TOC.-1b@ha
+    addi    %r2, %r2, .TOC.-1b@l

     /* set up the initial stack */
-    LOAD_IMM32(%r1, cpu0_boot_stack)
+    LOAD_REG_ADDR(%r1, cpu0_boot_stack)
     li      %r11, 0
     stdu    %r11, -STACK_FRAME_OVERHEAD(%r1)

     /* clear .bss */
-    LOAD_IMM32(%r14, __bss_start)
-    LOAD_IMM32(%r15, __bss_end)
+    LOAD_REG_ADDR(%r14, __bss_start)
+    LOAD_REG_ADDR(%r15, __bss_end)
 1:
     std     %r11, 0(%r14)
     addi    %r14, %r14, 8
diff --git a/xen/arch/ppc/xen.lds.S b/xen/arch/ppc/xen.lds.S
index c628cc0e5c..2fa81d5a83 100644
--- a/xen/arch/ppc/xen.lds.S
+++ b/xen/arch/ppc/xen.lds.S
@@ -15,25 +15,12 @@  PHDRS
 #endif
 }

-/**
- * OpenFirmware's base load address is 0x400000 (XEN_VIRT_START).
- * By defining sections this way, we can keep our virtual address base at 0x400000
- * while keeping the physical base at 0x0.
- *
- * Otherwise, OpenFirmware incorrectly loads .text at 0x400000 + 0x400000 = 0x800000.
- * Taken from x86/xen.lds.S
- */
-#ifdef CONFIG_LD_IS_GNU
-# define DECL_SECTION(x) x : AT(ADDR(#x) - XEN_VIRT_START)
-#else
-# define DECL_SECTION(x) x : AT(ADDR(x) - XEN_VIRT_START)
-#endif
-
 SECTIONS
 {
     . = XEN_VIRT_START;
+    _start = .;

-    DECL_SECTION(.text) {
+    .text : {
         _stext = .;            /* Text section */
         *(.text.header)

@@ -52,7 +39,7 @@  SECTIONS
     } :text

     . = ALIGN(PAGE_SIZE);
-    DECL_SECTION(.rodata) {
+    .rodata : {
         _srodata = .;          /* Read-only data */
         *(.rodata)
         *(.rodata.*)
@@ -67,7 +54,7 @@  SECTIONS

     #if defined(BUILD_ID)
     . = ALIGN(4);
-    DECL_SECTION(.note.gnu.build-id) {
+    .note.gnu.build-id : {
         __note_gnu_build_id_start = .;
         *(.note.gnu.build-id)
         __note_gnu_build_id_end = .;
@@ -76,19 +63,19 @@  SECTIONS
     _erodata = .;                /* End of read-only data */

     . = ALIGN(PAGE_SIZE);
-    DECL_SECTION(.data.ro_after_init) {
+    .data.ro_after_init : {
         __ro_after_init_start = .;
         *(.data.ro_after_init)
         . = ALIGN(PAGE_SIZE);
         __ro_after_init_end = .;
-    } : text
+    } :text

-    DECL_SECTION(.data.read_mostly) {
+    .data.read_mostly : {
         *(.data.read_mostly)
     } :text

     . = ALIGN(PAGE_SIZE);
-    DECL_SECTION(.data) {                    /* Data */
+    .data : {                    /* Data */
         *(.data.page_aligned)
         . = ALIGN(8);
         __start_schedulers_array = .;
@@ -103,7 +90,7 @@  SECTIONS

     . = ALIGN(PAGE_SIZE);             /* Init code and data */
     __init_begin = .;
-    DECL_SECTION(.init.text) {
+    .init.text : {
         _sinittext = .;
         *(.init.text)
         _einittext = .;
@@ -111,7 +98,7 @@  SECTIONS
     } :text

     . = ALIGN(PAGE_SIZE);
-    DECL_SECTION(.init.data) {
+    .init.data : {
         *(.init.rodata)
         *(.init.rodata.*)

@@ -140,18 +127,18 @@  SECTIONS
         __ctors_end = .;
     } :text

-    DECL_SECTION(.got) {
-        *(.got)
+    .got : {
+        *(.got .toc)
     } :text

-    DECL_SECTION(.got.plt) {
+    .got.plt : {
         *(.got.plt)
     } :text

     . = ALIGN(POINTER_ALIGN);
     __init_end = .;

-    DECL_SECTION(.bss) {                     /* BSS */
+    .bss : {                     /* BSS */
         __bss_start = .;
         *(.bss.stack_aligned)
         *(.bss.page_aligned)
@@ -167,10 +154,11 @@  SECTIONS
         . = ALIGN(POINTER_ALIGN);
         __bss_end = .;
     } :text
+
     _end = . ;

     /* Section for the device tree blob (if any). */
-    DECL_SECTION(.dtb) { *(.dtb) } :text
+    .dtb : { *(.dtb) } :text

     DWARF2_DEBUG_SECTIONS