| Message ID | 20230728041150.2524032-10-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DSC misc fixes | expand |
On Fri, Jul 28, 2023 at 09:41:39AM +0530, Ankit Nautiyal wrote: > For MST the bpc is hardcoded to 8, and pipe bpp to 24. > So avoid forcing DSC bpc for MST case. > > v2: Warn and ignore the debug flag than to bail out. (Jani) > > v3: Fix dbg message to mention forced bpc instead of bpp. > > v4: Fix checkpatch longline warning. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++ > 2 files changed, 11 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index c5d2e6f538ed..7ec8a478e000 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1697,14 +1697,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) > return -EINVAL; > > - if (compute_pipe_bpp) > + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) { > + pipe_bpp = intel_dp->force_dsc_bpc * 3; > + drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n", > + intel_dp->force_dsc_bpc); > + } else if (compute_pipe_bpp) { > pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); > - else > + } else { > pipe_bpp = pipe_config->pipe_bpp; > - > - if (intel_dp->force_dsc_bpc) { > - pipe_bpp = intel_dp->force_dsc_bpc * 3; > - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp); > } > > /* Min Input BPC for ICL+ is 8 */ > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 1f00713fb1ad..dff4717edbd0 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -361,6 +361,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, > /* enable compression if the mode doesn't fit available BW */ > drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); > if (ret || intel_dp->force_dsc_en) { > + /* > + * FIXME: As bpc is hardcoded to 8, as mentioned above, > + * WARN and ignore the debug flag force_dsc_bpc for now. > + */ > + drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n"); > /* > * Try to get at least some timeslots and then see, if > * we can fit there with DSC. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > -- > 2.40.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c5d2e6f538ed..7ec8a478e000 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1697,14 +1697,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) return -EINVAL; - if (compute_pipe_bpp) + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) { + pipe_bpp = intel_dp->force_dsc_bpc * 3; + drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n", + intel_dp->force_dsc_bpc); + } else if (compute_pipe_bpp) { pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); - else + } else { pipe_bpp = pipe_config->pipe_bpp; - - if (intel_dp->force_dsc_bpc) { - pipe_bpp = intel_dp->force_dsc_bpc * 3; - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp); } /* Min Input BPC for ICL+ is 8 */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1f00713fb1ad..dff4717edbd0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -361,6 +361,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, /* enable compression if the mode doesn't fit available BW */ drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); if (ret || intel_dp->force_dsc_en) { + /* + * FIXME: As bpc is hardcoded to 8, as mentioned above, + * WARN and ignore the debug flag force_dsc_bpc for now. + */ + drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n"); /* * Try to get at least some timeslots and then see, if * we can fit there with DSC.
For MST the bpc is hardcoded to 8, and pipe bpp to 24. So avoid forcing DSC bpc for MST case. v2: Warn and ignore the debug flag than to bail out. (Jani) v3: Fix dbg message to mention forced bpc instead of bpp. v4: Fix checkpatch longline warning. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------ drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++ 2 files changed, 11 insertions(+), 6 deletions(-)