| Message ID | 20230802122510.275420-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Fix Versa3 clock mapping | expand |
Hey Biju, On Wed, Aug 02, 2023 at 01:25:08PM +0100, Biju Das wrote: > Document clock-output-names property. Update the example according to > Table 3. ("Output Source") in the 5P35023 datasheet. > > While at it, replace clocks phandle in the example from x1_x2->x1 as > X2 is a different 32768 kHz crystal. > > Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> > Closes: https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpaejss0Y2ZpLCMNg@mail.gmail.com/ > Fixes: a03d23f860eb ("dt-bindings: clock: Add Renesas versa3 clock generator bindings") Nothing in this commit message explains why this is a fix for this binding addition :( > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > .../devicetree/bindings/clock/renesas,5p35023.yaml | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > index 839648e753d4..db8d01b291dd 100644 > --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > @@ -49,6 +49,9 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint8-array > maxItems: 37 > > + clock-output-names: > + maxItems: 6 > + > required: > - compatible > - reg > @@ -68,7 +71,7 @@ examples: > reg = <0x68>; > #clock-cells = <1>; > > - clocks = <&x1_x2>; > + clocks = <&x1>; > > renesas,settings = [ > 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf > @@ -76,11 +79,14 @@ examples: > 80 b0 45 c4 95 > ]; > > + clock-output-names = "ref", "se1", "se2", "se3", > + "diff1", "diff2"; > + > assigned-clocks = <&versa3 0>, <&versa3 1>, > <&versa3 2>, <&versa3 3>, > <&versa3 4>, <&versa3 5>; > - assigned-clock-rates = <12288000>, <25000000>, > - <12000000>, <11289600>, > - <11289600>, <24000000>; > + assigned-clock-rates = <24000000>, <11289600>, > + <11289600>, <12000000>, > + <25000000>, <12288000>; > }; > }; > -- > 2.25.1 >
Hi Conor Dooley, Thanks for the feedback. > Subject: Re: [PATCH 1/3] dt-bindings: clock: versaclock3: Document > clock-output-names > > Hey Biju, > > On Wed, Aug 02, 2023 at 01:25:08PM +0100, Biju Das wrote: > > Document clock-output-names property. Update the example according to > > Table 3. ("Output Source") in the 5P35023 datasheet. > > > > While at it, replace clocks phandle in the example from x1_x2->x1 as > > X2 is a different 32768 kHz crystal. > > > > Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Closes: > > https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpaejss0 > > Y2ZpLCMNg@mail.gmail.com/ > > Fixes: a03d23f860eb ("dt-bindings: clock: Add Renesas versa3 clock > > generator bindings") > > Nothing in this commit message explains why this is a fix for this > binding addition :( Basically, it fixes "assigned-clock-rates" for each clock output in the example. Now it is based on Table 3. ("Output Source") in the 5P35023 datasheet(ie: 0= REF, 1=SE1, 2=SE2, 3=SE3, 4=DIFF1, 5=DIFF2). The newly added clock-output-names in the example are based on the above table. I have added fixes tag, because this patch fixes the clock mapping in the example as per the HW manual. Please let me know should I drop fixes tag?? Cheers, Biju > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > .../devicetree/bindings/clock/renesas,5p35023.yaml | 14 > > ++++++++++---- > > 1 file changed, 10 insertions(+), 4 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > > b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > > index 839648e753d4..db8d01b291dd 100644 > > --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > > +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml > > @@ -49,6 +49,9 @@ properties: > > $ref: /schemas/types.yaml#/definitions/uint8-array > > maxItems: 37 > > > > + clock-output-names: > > + maxItems: 6 > > + > > required: > > - compatible > > - reg > > @@ -68,7 +71,7 @@ examples: > > reg = <0x68>; > > #clock-cells = <1>; > > > > - clocks = <&x1_x2>; > > + clocks = <&x1>; > > > > renesas,settings = [ > > 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf @@ > > -76,11 +79,14 @@ examples: > > 80 b0 45 c4 95 > > ]; > > > > + clock-output-names = "ref", "se1", "se2", "se3", > > + "diff1", "diff2"; > > + > > assigned-clocks = <&versa3 0>, <&versa3 1>, > > <&versa3 2>, <&versa3 3>, > > <&versa3 4>, <&versa3 5>; > > - assigned-clock-rates = <12288000>, <25000000>, > > - <12000000>, <11289600>, > > - <11289600>, <24000000>; > > + assigned-clock-rates = <24000000>, <11289600>, > > + <11289600>, <12000000>, > > + <25000000>, <12288000>; > > }; > > }; > > -- > > 2.25.1 > >
On Thu, Aug 03, 2023 at 04:25:40PM +0000, Biju Das wrote: > > Subject: Re: [PATCH 1/3] dt-bindings: clock: versaclock3: Document > > clock-output-names > > > > On Wed, Aug 02, 2023 at 01:25:08PM +0100, Biju Das wrote: > > > Document clock-output-names property. Update the example according to > > > Table 3. ("Output Source") in the 5P35023 datasheet. > > > > > > While at it, replace clocks phandle in the example from x1_x2->x1 as > > > X2 is a different 32768 kHz crystal. > > > > > > Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > Closes: > > > https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpaejss0 > > > Y2ZpLCMNg@mail.gmail.com/ > > > Fixes: a03d23f860eb ("dt-bindings: clock: Add Renesas versa3 clock > > > generator bindings") > > > > Nothing in this commit message explains why this is a fix for this > > binding addition :( > > Basically, it fixes "assigned-clock-rates" for each clock output in the example. Now it is based on Table 3. ("Output Source") in the 5P35023 datasheet(ie: 0= REF, 1=SE1, 2=SE2, 3=SE3, 4=DIFF1, 5=DIFF2). > > The newly added clock-output-names in the example are based on the above table. > > I have added fixes tag, because this patch fixes the clock mapping in the example as per the HW manual. > > Please let me know should I drop fixes tag?? I'm just asking for an explanation in the commit message as to what was actually wrong in the first place. The commit message says 3 things of which it's hard to know what is actually a fix without opening & reading the linked thread on lore. Cheers, Conor.
Hi Conor, Thanks for the feedback. > Subject: Re: [PATCH 1/3] dt-bindings: clock: versaclock3: Document > clock-output-names > > On Thu, Aug 03, 2023 at 04:25:40PM +0000, Biju Das wrote: > > > Subject: Re: [PATCH 1/3] dt-bindings: clock: versaclock3: Document > > > clock-output-names > > > > > > On Wed, Aug 02, 2023 at 01:25:08PM +0100, Biju Das wrote: > > > > Document clock-output-names property. Update the example according > > > > to Table 3. ("Output Source") in the 5P35023 datasheet. > > > > > > > > While at it, replace clocks phandle in the example from x1_x2->x1 > > > > as > > > > X2 is a different 32768 kHz crystal. > > > > > > > > Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > > Closes: > > > > https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpae > > > > jss0 > > > > Y2ZpLCMNg@mail.gmail.com/ > > > > Fixes: a03d23f860eb ("dt-bindings: clock: Add Renesas versa3 clock > > > > generator bindings") > > > > > > Nothing in this commit message explains why this is a fix for this > > > binding addition :( > > > > Basically, it fixes "assigned-clock-rates" for each clock output in > the example. Now it is based on Table 3. ("Output Source") in the > 5P35023 datasheet(ie: 0= REF, 1=SE1, 2=SE2, 3=SE3, 4=DIFF1, 5=DIFF2). > > > > The newly added clock-output-names in the example are based on the > above table. > > > > I have added fixes tag, because this patch fixes the clock mapping in > the example as per the HW manual. > > > > Please let me know should I drop fixes tag?? > > I'm just asking for an explanation in the commit message as to what was > actually wrong in the first place. The commit message says 3 things of > which it's hard to know what is actually a fix without opening & reading > the linked thread on lore. OK, Will explicitly mention it fixes "assigned-clock-rates" for each clock output in the example based on Table 3.("Output Source") in the 5P35023 datasheet. Cheers, Biju
diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml index 839648e753d4..db8d01b291dd 100644 --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml @@ -49,6 +49,9 @@ properties: $ref: /schemas/types.yaml#/definitions/uint8-array maxItems: 37 + clock-output-names: + maxItems: 6 + required: - compatible - reg @@ -68,7 +71,7 @@ examples: reg = <0x68>; #clock-cells = <1>; - clocks = <&x1_x2>; + clocks = <&x1>; renesas,settings = [ 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf @@ -76,11 +79,14 @@ examples: 80 b0 45 c4 95 ]; + clock-output-names = "ref", "se1", "se2", "se3", + "diff1", "diff2"; + assigned-clocks = <&versa3 0>, <&versa3 1>, <&versa3 2>, <&versa3 3>, <&versa3 4>, <&versa3 5>; - assigned-clock-rates = <12288000>, <25000000>, - <12000000>, <11289600>, - <11289600>, <24000000>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; }; };
Document clock-output-names property. Update the example according to Table 3. ("Output Source") in the 5P35023 datasheet. While at it, replace clocks phandle in the example from x1_x2->x1 as X2 is a different 32768 kHz crystal. Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> Closes: https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpaejss0Y2ZpLCMNg@mail.gmail.com/ Fixes: a03d23f860eb ("dt-bindings: clock: Add Renesas versa3 clock generator bindings") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../devicetree/bindings/clock/renesas,5p35023.yaml | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)