| Message ID | 20230808194811.113087-1-alexander.stein@mailbox.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/1] dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format | expand |
On Tue 08 Aug 2023 at 21:48, Alexander Stein <alexander.stein@mailbox.org> wrote: > Convert Amlogic AXG Audio Clock Controller binding to yaml. > > Signed-off-by: Alexander Stein <alexander.stein@mailbox.org> > --- > As it is the same directory I picked the same maintainers as > Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml. > > I'm not 100% sure about the optional clocks constraints. As mentioned in > the .txt version only pclk is mandatory, others are optional. > > .../bindings/clock/amlogic,axg-audio-clkc.txt | 59 -------- > .../clock/amlogic,axg-audio-clkc.yaml | 136 ++++++++++++++++++ > 2 files changed, 136 insertions(+), 59 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt > deleted file mode 100644 > index 3a8948c04bc9..000000000000 > --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt > +++ /dev/null > @@ -1,59 +0,0 @@ > -* Amlogic AXG Audio Clock Controllers > - > -The Amlogic AXG audio clock controller generates and supplies clock to the > -other elements of the audio subsystem, such as fifos, i2s, spdif and pdm > -devices. > - > -Required Properties: > - > -- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, > - "amlogic,g12a-audio-clkc" for G12A, > - "amlogic,sm1-audio-clkc" for S905X3. > -- reg : physical base address of the clock controller and length of > - memory mapped region. > -- clocks : a list of phandle + clock-specifier pairs for the clocks listed > - in clock-names. > -- clock-names : must contain the following: > - * "pclk" - Main peripheral bus clock > - may contain the following: > - * "mst_in[0-7]" - 8 input plls to generate clock signals > - * "slv_sclk[0-9]" - 10 slave bit clocks provided by external > - components. > - * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external > - components. > -- resets : phandle of the internal reset line > -- #clock-cells : should be 1. > -- #reset-cells : should be 1 on the g12a (and following) soc family > - > -Each clock is assigned an identifier and client nodes can use this identifier > -to specify the clock which they consume. All available clocks are defined as > -preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be > -used in device tree sources. > - > -Example: > - > -clkc_audio: clock-controller@0 { > - compatible = "amlogic,axg-audio-clkc"; > - reg = <0x0 0x0 0x0 0xb4>; > - #clock-cells = <1>; > - > - clocks = <&clkc CLKID_AUDIO>, > - <&clkc CLKID_MPLL0>, > - <&clkc CLKID_MPLL1>, > - <&clkc CLKID_MPLL2>, > - <&clkc CLKID_MPLL3>, > - <&clkc CLKID_HIFI_PLL>, > - <&clkc CLKID_FCLK_DIV3>, > - <&clkc CLKID_FCLK_DIV4>, > - <&clkc CLKID_GP0_PLL>; > - clock-names = "pclk", > - "mst_in0", > - "mst_in1", > - "mst_in2", > - "mst_in3", > - "mst_in4", > - "mst_in5", > - "mst_in6", > - "mst_in7"; > - resets = <&reset RESET_AUDIO>; > -}; > diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > new file mode 100644 > index 000000000000..629fa3a81cf7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > @@ -0,0 +1,136 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Amlogic AXG Audio Clock Controller > + > +maintainers: > + - Neil Armstrong <neil.armstrong@linaro.org> > + - Jerome Brunet <jbrunet@baylibre.com> > + - Jian Hu <jian.hu@jian.hu.com> > + - Dmitry Rokosov <ddrokosov@sberdevices.ru> > + Jian and Dmitry do not maintain this. > +description: > + The Amlogic AXG audio clock controller generates and supplies clock to the > + other elements of the audio subsystem, such as fifos, i2s, spdif and pdm > + devices. > + > +properties: > + compatible: > + enum: > + - amlogic,axg-audio-clkc > + - amlogic,g12a-audio-clkc > + - amlogic,sm1-audio-clkc > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 11 > + > + clock-names: > + oneOf: > + - const: pclk > + - items: > + - const: pclk > + - const: mst_in0 > + - const: mst_in1 > + - const: mst_in2 > + - const: mst_in3 > + - const: mst_in4 > + - const: mst_in5 > + - const: mst_in6 > + - const: mst_in7 > + - items: > + - const: pclk > + - const: slv_sclk0 > + - const: slv_sclk1 > + - const: slv_sclk2 > + - const: slv_sclk3 > + - const: slv_sclk4 > + - const: slv_sclk5 > + - const: slv_sclk6 > + - const: slv_sclk7 > + - const: slv_sclk8 > + - const: slv_sclk9 > + - items: > + - const: pclk > + - const: slv_lrclk0 > + - const: slv_lrclk1 > + - const: slv_lrclk2 > + - const: slv_lrclk3 > + - const: slv_lrclk4 > + - const: slv_lrclk5 > + - const: slv_lrclk6 > + - const: slv_lrclk7 > + - const: slv_lrclk8 > + - const: slv_lrclk9 > + IIUC the above, it means - pclk - OR pclk with all the master clocks - OR pclk with all the slave bit clocks - OR pclk with all the slave sample clocks. Correct ? If that is what it means, it is wrong. * pclk is required * the master and slave clocks are all optional and independent. Any combination of master and slave clocks is valid from the controller perspective. For ex: it is perfectly OK to have master 2 and 4, slave 5 and 8, and not the others. > + resets: > + description: internal reset line > + > +required: > + - compatible > + - '#clock-cells' > + - reg > + - clocks > + - clock-names > + - resets > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - amlogic,g12a-audio-clkc > + - amlogic,sm1-audio-clkc > + then: > + required: > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/axg-clkc.h> > + #include <dt-bindings/reset/amlogic,meson-axg-reset.h> > + apb { > + #address-cells = <2>; > + #size-cells = <2>; > + > + clkc_audio: clock-controller@0 { > + compatible = "amlogic,axg-audio-clkc"; > + reg = <0x0 0x0 0x0 0xb4>; > + #clock-cells = <1>; > + > + clocks = <&clkc CLKID_AUDIO>, > + <&clkc CLKID_MPLL0>, > + <&clkc CLKID_MPLL1>, > + <&clkc CLKID_MPLL2>, > + <&clkc CLKID_MPLL3>, > + <&clkc CLKID_HIFI_PLL>, > + <&clkc CLKID_FCLK_DIV3>, > + <&clkc CLKID_FCLK_DIV4>, > + <&clkc CLKID_GP0_PLL>; > + clock-names = "pclk", > + "mst_in0", > + "mst_in1", > + "mst_in2", > + "mst_in3", > + "mst_in4", > + "mst_in5", > + "mst_in6", > + "mst_in7"; > + resets = <&reset RESET_AUDIO>; > + }; > + };
On 08/08/2023 21:48, Alexander Stein wrote: > Convert Amlogic AXG Audio Clock Controller binding to yaml. > > Signed-off-by: Alexander Stein <alexander.stein@mailbox.org> > --- > As it is the same directory I picked the same maintainers as > Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml. > > I'm not 100% sure about the optional clocks constraints. As mentioned in > the .txt version only pclk is mandatory, others are optional. > > .../bindings/clock/amlogic,axg-audio-clkc.txt | 59 -------- > .../clock/amlogic,axg-audio-clkc.yaml | 136 ++++++++++++++++++ > 2 files changed, 136 insertions(+), 59 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt > deleted file mode 100644 > index 3a8948c04bc9..000000000000 > --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt > +++ /dev/null > @@ -1,59 +0,0 @@ > -* Amlogic AXG Audio Clock Controllers > - > -The Amlogic AXG audio clock controller generates and supplies clock to the > -other elements of the audio subsystem, such as fifos, i2s, spdif and pdm > -devices. > - > -Required Properties: > - > -- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, > - "amlogic,g12a-audio-clkc" for G12A, > - "amlogic,sm1-audio-clkc" for S905X3. > -- reg : physical base address of the clock controller and length of > - memory mapped region. > -- clocks : a list of phandle + clock-specifier pairs for the clocks listed > - in clock-names. > -- clock-names : must contain the following: > - * "pclk" - Main peripheral bus clock > - may contain the following: > - * "mst_in[0-7]" - 8 input plls to generate clock signals > - * "slv_sclk[0-9]" - 10 slave bit clocks provided by external > - components. > - * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external > - components. > -- resets : phandle of the internal reset line > -- #clock-cells : should be 1. > -- #reset-cells : should be 1 on the g12a (and following) soc family > - > -Each clock is assigned an identifier and client nodes can use this identifier > -to specify the clock which they consume. All available clocks are defined as > -preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be > -used in device tree sources. > - > -Example: > - > -clkc_audio: clock-controller@0 { > - compatible = "amlogic,axg-audio-clkc"; > - reg = <0x0 0x0 0x0 0xb4>; > - #clock-cells = <1>; > - > - clocks = <&clkc CLKID_AUDIO>, > - <&clkc CLKID_MPLL0>, > - <&clkc CLKID_MPLL1>, > - <&clkc CLKID_MPLL2>, > - <&clkc CLKID_MPLL3>, > - <&clkc CLKID_HIFI_PLL>, > - <&clkc CLKID_FCLK_DIV3>, > - <&clkc CLKID_FCLK_DIV4>, > - <&clkc CLKID_GP0_PLL>; > - clock-names = "pclk", > - "mst_in0", > - "mst_in1", > - "mst_in2", > - "mst_in3", > - "mst_in4", > - "mst_in5", > - "mst_in6", > - "mst_in7"; > - resets = <&reset RESET_AUDIO>; > -}; > diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > new file mode 100644 > index 000000000000..629fa3a81cf7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > @@ -0,0 +1,136 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Amlogic AXG Audio Clock Controller > + > +maintainers: > + - Neil Armstrong <neil.armstrong@linaro.org> > + - Jerome Brunet <jbrunet@baylibre.com> > + - Jian Hu <jian.hu@jian.hu.com> > + - Dmitry Rokosov <ddrokosov@sberdevices.ru> > + > +description: > + The Amlogic AXG audio clock controller generates and supplies clock to the > + other elements of the audio subsystem, such as fifos, i2s, spdif and pdm > + devices. > + > +properties: > + compatible: > + enum: > + - amlogic,axg-audio-clkc > + - amlogic,g12a-audio-clkc > + - amlogic,sm1-audio-clkc > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > + reg: > + maxItems: 1 reg is usually the second property. > + > + clocks: > + minItems: 1 > + maxItems: 11 > + > + clock-names: > + oneOf: > + - const: pclk > + - items: > + - const: pclk > + - const: mst_in0 > + - const: mst_in1 > + - const: mst_in2 > + - const: mst_in3 > + - const: mst_in4 > + - const: mst_in5 > + - const: mst_in6 > + - const: mst_in7 > + - items: > + - const: pclk > + - const: slv_sclk0 > + - const: slv_sclk1 > + - const: slv_sclk2 > + - const: slv_sclk3 > + - const: slv_sclk4 > + - const: slv_sclk5 > + - const: slv_sclk6 > + - const: slv_sclk7 > + - const: slv_sclk8 > + - const: slv_sclk9 > + - items: > + - const: pclk > + - const: slv_lrclk0 > + - const: slv_lrclk1 > + - const: slv_lrclk2 > + - const: slv_lrclk3 > + - const: slv_lrclk4 > + - const: slv_lrclk5 > + - const: slv_lrclk6 > + - const: slv_lrclk7 > + - const: slv_lrclk8 > + - const: slv_lrclk9 > + > + resets: > + description: internal reset line > + > +required: > + - compatible > + - '#clock-cells' > + - reg > + - clocks > + - clock-names > + - resets > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - amlogic,g12a-audio-clkc > + - amlogic,sm1-audio-clkc > + then: > + required: > + - '#reset-cells' else: properties: '#reset-cells': false ??? You need to constrain the clocks per variant. Probably names are also specific to each one, so the list of names can be moved here and you keep just min/maxItems in the top level property. > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/axg-clkc.h> > + #include <dt-bindings/reset/amlogic,meson-axg-reset.h> > + apb { > + #address-cells = <2>; > + #size-cells = <2>; > + > + clkc_audio: clock-controller@0 { > + compatible = "amlogic,axg-audio-clkc"; Broken indentation. > + reg = <0x0 0x0 0x0 0xb4>; > + #clock-cells = <1>; > + > + clocks = <&clkc CLKID_AUDIO>, > + <&clkc CLKID_MPLL0>, > + <&clkc CLKID_MPLL1>, > + <&clkc CLKID_MPLL2>, > + <&clkc CLKID_MPLL3>, > + <&clkc CLKID_HIFI_PLL>, > + <&clkc CLKID_FCLK_DIV3>, > + <&clkc CLKID_FCLK_DIV4>, > + <&clkc CLKID_GP0_PLL>; > + clock-names = "pclk", > + "mst_in0", > + "mst_in1", > + "mst_in2", > + "mst_in3", > + "mst_in4", > + "mst_in5", > + "mst_in6", > + "mst_in7"; > + resets = <&reset RESET_AUDIO>; > + }; And indentation here is even less matching. > + }; Best regards, Krzysztof
On Wed 09 Aug 2023 at 08:38, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 08/08/2023 21:48, Alexander Stein wrote: >> Convert Amlogic AXG Audio Clock Controller binding to yaml. >> >> Signed-off-by: Alexander Stein <alexander.stein@mailbox.org> >> --- >> As it is the same directory I picked the same maintainers as >> Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml. >> >> I'm not 100% sure about the optional clocks constraints. As mentioned in >> the .txt version only pclk is mandatory, others are optional. >> >> .../bindings/clock/amlogic,axg-audio-clkc.txt | 59 -------- >> .../clock/amlogic,axg-audio-clkc.yaml | 136 ++++++++++++++++++ >> 2 files changed, 136 insertions(+), 59 deletions(-) >> delete mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt >> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> >> diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt >> deleted file mode 100644 >> index 3a8948c04bc9..000000000000 >> --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt >> +++ /dev/null >> @@ -1,59 +0,0 @@ >> -* Amlogic AXG Audio Clock Controllers >> - >> -The Amlogic AXG audio clock controller generates and supplies clock to the >> -other elements of the audio subsystem, such as fifos, i2s, spdif and pdm >> -devices. >> - >> -Required Properties: >> - >> -- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, >> - "amlogic,g12a-audio-clkc" for G12A, >> - "amlogic,sm1-audio-clkc" for S905X3. >> -- reg : physical base address of the clock controller and length of >> - memory mapped region. >> -- clocks : a list of phandle + clock-specifier pairs for the clocks listed >> - in clock-names. >> -- clock-names : must contain the following: >> - * "pclk" - Main peripheral bus clock >> - may contain the following: >> - * "mst_in[0-7]" - 8 input plls to generate clock signals >> - * "slv_sclk[0-9]" - 10 slave bit clocks provided by external >> - components. >> - * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external >> - components. >> -- resets : phandle of the internal reset line >> -- #clock-cells : should be 1. >> -- #reset-cells : should be 1 on the g12a (and following) soc family >> - >> -Each clock is assigned an identifier and client nodes can use this identifier >> -to specify the clock which they consume. All available clocks are defined as >> -preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be >> -used in device tree sources. >> - >> -Example: >> - >> -clkc_audio: clock-controller@0 { >> - compatible = "amlogic,axg-audio-clkc"; >> - reg = <0x0 0x0 0x0 0xb4>; >> - #clock-cells = <1>; >> - >> - clocks = <&clkc CLKID_AUDIO>, >> - <&clkc CLKID_MPLL0>, >> - <&clkc CLKID_MPLL1>, >> - <&clkc CLKID_MPLL2>, >> - <&clkc CLKID_MPLL3>, >> - <&clkc CLKID_HIFI_PLL>, >> - <&clkc CLKID_FCLK_DIV3>, >> - <&clkc CLKID_FCLK_DIV4>, >> - <&clkc CLKID_GP0_PLL>; >> - clock-names = "pclk", >> - "mst_in0", >> - "mst_in1", >> - "mst_in2", >> - "mst_in3", >> - "mst_in4", >> - "mst_in5", >> - "mst_in6", >> - "mst_in7"; >> - resets = <&reset RESET_AUDIO>; >> -}; >> diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> new file mode 100644 >> index 000000000000..629fa3a81cf7 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> @@ -0,0 +1,136 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Amlogic AXG Audio Clock Controller >> + >> +maintainers: >> + - Neil Armstrong <neil.armstrong@linaro.org> >> + - Jerome Brunet <jbrunet@baylibre.com> >> + - Jian Hu <jian.hu@jian.hu.com> >> + - Dmitry Rokosov <ddrokosov@sberdevices.ru> >> + >> +description: >> + The Amlogic AXG audio clock controller generates and supplies clock to the >> + other elements of the audio subsystem, such as fifos, i2s, spdif and pdm >> + devices. >> + >> +properties: >> + compatible: >> + enum: >> + - amlogic,axg-audio-clkc >> + - amlogic,g12a-audio-clkc >> + - amlogic,sm1-audio-clkc >> + >> + '#clock-cells': >> + const: 1 >> + >> + '#reset-cells': >> + const: 1 >> + >> + reg: >> + maxItems: 1 > > reg is usually the second property. > >> + >> + clocks: >> + minItems: 1 >> + maxItems: 11 >> + >> + clock-names: >> + oneOf: >> + - const: pclk >> + - items: >> + - const: pclk >> + - const: mst_in0 >> + - const: mst_in1 >> + - const: mst_in2 >> + - const: mst_in3 >> + - const: mst_in4 >> + - const: mst_in5 >> + - const: mst_in6 >> + - const: mst_in7 >> + - items: >> + - const: pclk >> + - const: slv_sclk0 >> + - const: slv_sclk1 >> + - const: slv_sclk2 >> + - const: slv_sclk3 >> + - const: slv_sclk4 >> + - const: slv_sclk5 >> + - const: slv_sclk6 >> + - const: slv_sclk7 >> + - const: slv_sclk8 >> + - const: slv_sclk9 >> + - items: >> + - const: pclk >> + - const: slv_lrclk0 >> + - const: slv_lrclk1 >> + - const: slv_lrclk2 >> + - const: slv_lrclk3 >> + - const: slv_lrclk4 >> + - const: slv_lrclk5 >> + - const: slv_lrclk6 >> + - const: slv_lrclk7 >> + - const: slv_lrclk8 >> + - const: slv_lrclk9 >> + >> + resets: >> + description: internal reset line >> + >> +required: >> + - compatible >> + - '#clock-cells' >> + - reg >> + - clocks >> + - clock-names >> + - resets >> + >> +allOf: >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - amlogic,g12a-audio-clkc >> + - amlogic,sm1-audio-clkc >> + then: >> + required: >> + - '#reset-cells' > > else: > properties: > '#reset-cells': false > ??? > > > You need to constrain the clocks per variant. Probably names are also > specific to each one, so the list of names can be moved here and you > keep just min/maxItems in the top level property. > input clock names and constraints are the same for all 3 variants. >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/axg-clkc.h> >> + #include <dt-bindings/reset/amlogic,meson-axg-reset.h> >> + apb { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + clkc_audio: clock-controller@0 { >> + compatible = "amlogic,axg-audio-clkc"; > > Broken indentation. > >> + reg = <0x0 0x0 0x0 0xb4>; >> + #clock-cells = <1>; >> + >> + clocks = <&clkc CLKID_AUDIO>, >> + <&clkc CLKID_MPLL0>, >> + <&clkc CLKID_MPLL1>, >> + <&clkc CLKID_MPLL2>, >> + <&clkc CLKID_MPLL3>, >> + <&clkc CLKID_HIFI_PLL>, >> + <&clkc CLKID_FCLK_DIV3>, >> + <&clkc CLKID_FCLK_DIV4>, >> + <&clkc CLKID_GP0_PLL>; >> + clock-names = "pclk", >> + "mst_in0", >> + "mst_in1", >> + "mst_in2", >> + "mst_in3", >> + "mst_in4", >> + "mst_in5", >> + "mst_in6", >> + "mst_in7"; >> + resets = <&reset RESET_AUDIO>; >> + }; > > And indentation here is even less matching. >> + }; > > Best regards, > Krzysztof
On 09/08/2023 08:58, Jerome Brunet wrote: >>> + required: >>> + - '#reset-cells' >> >> else: >> properties: >> '#reset-cells': false >> ??? >> >> >> You need to constrain the clocks per variant. Probably names are also >> specific to each one, so the list of names can be moved here and you >> keep just min/maxItems in the top level property. >> > > input clock names and constraints are the same for all 3 variants. Then why do you have this huge, apparently unnecessary, oneOf? If it's the same, then drop the oneOf and make number of clocks fixed. Best regards, Krzysztof
On Wed 09 Aug 2023 at 15:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 09/08/2023 08:58, Jerome Brunet wrote: >>>> + required: >>>> + - '#reset-cells' >>> >>> else: >>> properties: >>> '#reset-cells': false >>> ??? >>> >>> >>> You need to constrain the clocks per variant. Probably names are also >>> specific to each one, so the list of names can be moved here and you >>> keep just min/maxItems in the top level property. >>> >> >> input clock names and constraints are the same for all 3 variants. > > Then why do you have this huge, apparently unnecessary, oneOf? If it's > the same, then drop the oneOf and make number of clocks fixed. > As I pointed out, this section is wrong. > > Best regards, > Krzysztof
On 09/08/2023 15:46, Jerome Brunet wrote: > > On Wed 09 Aug 2023 at 15:02, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > >> On 09/08/2023 08:58, Jerome Brunet wrote: >>>>> + required: >>>>> + - '#reset-cells' >>>> >>>> else: >>>> properties: >>>> '#reset-cells': false >>>> ??? >>>> >>>> >>>> You need to constrain the clocks per variant. Probably names are also >>>> specific to each one, so the list of names can be moved here and you >>>> keep just min/maxItems in the top level property. >>>> >>> >>> input clock names and constraints are the same for all 3 variants. >> >> Then why do you have this huge, apparently unnecessary, oneOf? If it's >> the same, then drop the oneOf and make number of clocks fixed. >> > > As I pointed out, this section is wrong. Ah, I misunderstood. Looks good, thanks. Best regards, Krzysztof
Hi, Am Mittwoch, 9. August 2023, 08:15:31 CEST schrieb Jerome Brunet: > > On Tue 08 Aug 2023 at 21:48, Alexander Stein <alexander.stein@mailbox.org> wrote: > > > Convert Amlogic AXG Audio Clock Controller binding to yaml. > > > > Signed-off-by: Alexander Stein <alexander.stein@mailbox.org> > > --- > > As it is the same directory I picked the same maintainers as > > Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml. > > > > I'm not 100% sure about the optional clocks constraints. As mentioned in > > the .txt version only pclk is mandatory, others are optional. > > > > .../bindings/clock/amlogic,axg-audio-clkc.txt | 59 -------- > > .../clock/amlogic,axg-audio-clkc.yaml | 136 ++++++++++++++++++ > > 2 files changed, 136 insertions(+), 59 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt > > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt > > deleted file mode 100644 > > index 3a8948c04bc9..000000000000 > > --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt > > +++ /dev/null > > @@ -1,59 +0,0 @@ > > -* Amlogic AXG Audio Clock Controllers > > - > > -The Amlogic AXG audio clock controller generates and supplies clock to the > > -other elements of the audio subsystem, such as fifos, i2s, spdif and pdm > > -devices. > > - > > -Required Properties: > > - > > -- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, > > - "amlogic,g12a-audio-clkc" for G12A, > > - "amlogic,sm1-audio-clkc" for S905X3. > > -- reg : physical base address of the clock controller and length of > > - memory mapped region. > > -- clocks : a list of phandle + clock-specifier pairs for the clocks listed > > - in clock-names. > > -- clock-names : must contain the following: > > - * "pclk" - Main peripheral bus clock > > - may contain the following: > > - * "mst_in[0-7]" - 8 input plls to generate clock signals > > - * "slv_sclk[0-9]" - 10 slave bit clocks provided by external > > - components. > > - * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external > > - components. > > -- resets : phandle of the internal reset line > > -- #clock-cells : should be 1. > > -- #reset-cells : should be 1 on the g12a (and following) soc family > > - > > -Each clock is assigned an identifier and client nodes can use this identifier > > -to specify the clock which they consume. All available clocks are defined as > > -preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be > > -used in device tree sources. > > - > > -Example: > > - > > -clkc_audio: clock-controller@0 { > > - compatible = "amlogic,axg-audio-clkc"; > > - reg = <0x0 0x0 0x0 0xb4>; > > - #clock-cells = <1>; > > - > > - clocks = <&clkc CLKID_AUDIO>, > > - <&clkc CLKID_MPLL0>, > > - <&clkc CLKID_MPLL1>, > > - <&clkc CLKID_MPLL2>, > > - <&clkc CLKID_MPLL3>, > > - <&clkc CLKID_HIFI_PLL>, > > - <&clkc CLKID_FCLK_DIV3>, > > - <&clkc CLKID_FCLK_DIV4>, > > - <&clkc CLKID_GP0_PLL>; > > - clock-names = "pclk", > > - "mst_in0", > > - "mst_in1", > > - "mst_in2", > > - "mst_in3", > > - "mst_in4", > > - "mst_in5", > > - "mst_in6", > > - "mst_in7"; > > - resets = <&reset RESET_AUDIO>; > > -}; > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > > new file mode 100644 > > index 000000000000..629fa3a81cf7 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > > @@ -0,0 +1,136 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Amlogic AXG Audio Clock Controller > > + > > +maintainers: > > + - Neil Armstrong <neil.armstrong@linaro.org> > > + - Jerome Brunet <jbrunet@baylibre.com> > > + - Jian Hu <jian.hu@jian.hu.com> > > + - Dmitry Rokosov <ddrokosov@sberdevices.ru> > > + > > Jian and Dmitry do not maintain this. Okay, I'll remove them. > > +description: > > + The Amlogic AXG audio clock controller generates and supplies clock to the > > + other elements of the audio subsystem, such as fifos, i2s, spdif and pdm > > + devices. > > + > > +properties: > > + compatible: > > + enum: > > + - amlogic,axg-audio-clkc > > + - amlogic,g12a-audio-clkc > > + - amlogic,sm1-audio-clkc > > + > > + '#clock-cells': > > + const: 1 > > + > > + '#reset-cells': > > + const: 1 > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 1 > > + maxItems: 11 > > + > > + clock-names: > > + oneOf: > > + - const: pclk > > + - items: > > + - const: pclk > > + - const: mst_in0 > > + - const: mst_in1 > > + - const: mst_in2 > > + - const: mst_in3 > > + - const: mst_in4 > > + - const: mst_in5 > > + - const: mst_in6 > > + - const: mst_in7 > > + - items: > > + - const: pclk > > + - const: slv_sclk0 > > + - const: slv_sclk1 > > + - const: slv_sclk2 > > + - const: slv_sclk3 > > + - const: slv_sclk4 > > + - const: slv_sclk5 > > + - const: slv_sclk6 > > + - const: slv_sclk7 > > + - const: slv_sclk8 > > + - const: slv_sclk9 > > + - items: > > + - const: pclk > > + - const: slv_lrclk0 > > + - const: slv_lrclk1 > > + - const: slv_lrclk2 > > + - const: slv_lrclk3 > > + - const: slv_lrclk4 > > + - const: slv_lrclk5 > > + - const: slv_lrclk6 > > + - const: slv_lrclk7 > > + - const: slv_lrclk8 > > + - const: slv_lrclk9 > > + > > IIUC the above, it means > - pclk > - OR pclk with all the master clocks > - OR pclk with all the slave bit clocks > - OR pclk with all the slave sample clocks. > > Correct ? Yes, that's how I understood the txt binding. > If that is what it means, it is wrong. > > * pclk is required > * the master and slave clocks are all optional and independent. > > Any combination of master and slave clocks is valid from the controller > perspective. For ex: it is perfectly OK to have master 2 and 4, slave 5 > and 8, and not the others. Okay, this was not obvious to me from the textual description. Best regards, Alexander > > + resets: > > + description: internal reset line > > + > > +required: > > + - compatible > > + - '#clock-cells' > > + - reg > > + - clocks > > + - clock-names > > + - resets > > + > > +allOf: > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - amlogic,g12a-audio-clkc > > + - amlogic,sm1-audio-clkc > > + then: > > + required: > > + - '#reset-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/axg-clkc.h> > > + #include <dt-bindings/reset/amlogic,meson-axg-reset.h> > > + apb { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + clkc_audio: clock-controller@0 { > > + compatible = "amlogic,axg-audio-clkc"; > > + reg = <0x0 0x0 0x0 0xb4>; > > + #clock-cells = <1>; > > + > > + clocks = <&clkc CLKID_AUDIO>, > > + <&clkc CLKID_MPLL0>, > > + <&clkc CLKID_MPLL1>, > > + <&clkc CLKID_MPLL2>, > > + <&clkc CLKID_MPLL3>, > > + <&clkc CLKID_HIFI_PLL>, > > + <&clkc CLKID_FCLK_DIV3>, > > + <&clkc CLKID_FCLK_DIV4>, > > + <&clkc CLKID_GP0_PLL>; > > + clock-names = "pclk", > > + "mst_in0", > > + "mst_in1", > > + "mst_in2", > > + "mst_in3", > > + "mst_in4", > > + "mst_in5", > > + "mst_in6", > > + "mst_in7"; > > + resets = <&reset RESET_AUDIO>; > > + }; > > + }; > >
Hi, Am Mittwoch, 9. August 2023, 15:02:23 CEST schrieb Krzysztof Kozlowski: > On 09/08/2023 08:58, Jerome Brunet wrote: > >>> + required: > >>> + - '#reset-cells' > >> > >> else: > >> properties: > >> '#reset-cells': false > >> ??? > >> > >> > >> You need to constrain the clocks per variant. Probably names are also > >> specific to each one, so the list of names can be moved here and you > >> keep just min/maxItems in the top level property. > >> > > > > input clock names and constraints are the same for all 3 variants. > > Then why do you have this huge, apparently unnecessary, oneOf? If it's > the same, then drop the oneOf and make number of clocks fixed. But as far as I understand the number of clocks is not fixed. As Jerome pointed out in the other post, it can have any combination of clocks and range from 1 up to 11, where 'pclk' is always 1st clock. I currently have no idea how to constraint that, despite limiting the number of clock-names. Best regards, Alexander
On 09/08/2023 20:44, Alexander Stein wrote: > Hi, > > Am Mittwoch, 9. August 2023, 15:02:23 CEST schrieb Krzysztof Kozlowski: >> On 09/08/2023 08:58, Jerome Brunet wrote: >>>>> + required: >>>>> + - '#reset-cells' >>>> >>>> else: >>>> properties: >>>> '#reset-cells': false >>>> ??? >>>> >>>> >>>> You need to constrain the clocks per variant. Probably names are also >>>> specific to each one, so the list of names can be moved here and you >>>> keep just min/maxItems in the top level property. >>>> >>> >>> input clock names and constraints are the same for all 3 variants. >> >> Then why do you have this huge, apparently unnecessary, oneOf? If it's >> the same, then drop the oneOf and make number of clocks fixed. > > But as far as I understand the number of clocks is not fixed. As Jerome pointed > out in the other post, it can have any combination of clocks and range from 1 > up to 11, where 'pclk' is always 1st clock. > I currently have no idea how to constraint that, despite limiting the number > of clock-names. The same as in all other clock controllers (was also present on my list of useful patterns - Variable length arrays (per variant)): https://elixir.bootlin.com/linux/v5.19-rc6/source/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml#L57 Best regards, Krzysztof
On Thu 10 Aug 2023 at 08:11, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 09/08/2023 20:44, Alexander Stein wrote: >> Hi, >> >> Am Mittwoch, 9. August 2023, 15:02:23 CEST schrieb Krzysztof Kozlowski: >>> On 09/08/2023 08:58, Jerome Brunet wrote: >>>>>> + required: >>>>>> + - '#reset-cells' >>>>> >>>>> else: >>>>> properties: >>>>> '#reset-cells': false >>>>> ??? >>>>> >>>>> >>>>> You need to constrain the clocks per variant. Probably names are also >>>>> specific to each one, so the list of names can be moved here and you >>>>> keep just min/maxItems in the top level property. >>>>> >>>> >>>> input clock names and constraints are the same for all 3 variants. >>> >>> Then why do you have this huge, apparently unnecessary, oneOf? If it's >>> the same, then drop the oneOf and make number of clocks fixed. >> >> But as far as I understand the number of clocks is not fixed. As Jerome pointed >> out in the other post, it can have any combination of clocks and range from 1 >> up to 11, where 'pclk' is always 1st clock. >> I currently have no idea how to constraint that, despite limiting the number >> of clock-names. > > The same as in all other clock controllers (was also present on my list > of useful patterns - Variable length arrays (per variant)): > https://elixir.bootlin.com/linux/v5.19-rc6/source/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml#L57 In the example provided, the number and list of clocks required by each controller variant is fixed, if I'm reading it correctly Here the controller (regardless of the variant) accepts a maximum 29 clock inputs. Only pclk is required. It is valid to have any of 28 optional clocks at index 2, 3, etc ... I guess the question is how do you recommend to model that ? I can think of 'Anyof' with all the optional clocks repeated 28 times but that would be fairly ugly. > > Best regards, > Krzysztof
On 10/08/2023 09:32, Jerome Brunet wrote: >>>> Then why do you have this huge, apparently unnecessary, oneOf? If it's >>>> the same, then drop the oneOf and make number of clocks fixed. >>> >>> But as far as I understand the number of clocks is not fixed. As Jerome pointed >>> out in the other post, it can have any combination of clocks and range from 1 >>> up to 11, where 'pclk' is always 1st clock. >>> I currently have no idea how to constraint that, despite limiting the number >>> of clock-names. >> >> The same as in all other clock controllers (was also present on my list >> of useful patterns - Variable length arrays (per variant)): >> https://elixir.bootlin.com/linux/v5.19-rc6/source/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml#L57 > > In the example provided, the number and list of clocks required by each > controller variant is fixed, if I'm reading it correctly > > Here the controller (regardless of the variant) accepts a maximum 29 > clock inputs. Only pclk is required. It is valid to have any of 28 > optional clocks at index 2, 3, etc ... I actually doubt that it is optional. These are valid clock inputs. I could imagine they are optional depending on the use-case, like some block being turned off or on... but then still the clock is there, just not actively used. Aren't you now describing existing Linux driver? > I guess the question is how do you recommend to model that ? > I can think of 'Anyof' with all the optional clocks repeated 28 times > but that would be fairly ugly. Best regards, Krzysztof
On Thu 10 Aug 2023 at 09:46, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 10/08/2023 09:32, Jerome Brunet wrote: >>>>> Then why do you have this huge, apparently unnecessary, oneOf? If it's >>>>> the same, then drop the oneOf and make number of clocks fixed. >>>> >>>> But as far as I understand the number of clocks is not fixed. As Jerome pointed >>>> out in the other post, it can have any combination of clocks and range from 1 >>>> up to 11, where 'pclk' is always 1st clock. >>>> I currently have no idea how to constraint that, despite limiting the number >>>> of clock-names. >>> >>> The same as in all other clock controllers (was also present on my list >>> of useful patterns - Variable length arrays (per variant)): >>> https://elixir.bootlin.com/linux/v5.19-rc6/source/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml#L57 >> >> In the example provided, the number and list of clocks required by each >> controller variant is fixed, if I'm reading it correctly >> >> Here the controller (regardless of the variant) accepts a maximum 29 >> clock inputs. Only pclk is required. It is valid to have any of 28 >> optional clocks at index 2, 3, etc ... > > I actually doubt that it is optional. These are valid clock inputs. I > could imagine they are optional depending on the use-case, like some > block being turned off or on... but then still the clock is there, just > not actively used. > > Aren't you now describing existing Linux driver? They are valid inputs but not required. It is valid (and expected) to have a fair share of them not connected. The slave clocks just don't exist most of the time, and the IP can totally accept unwired master clock inputs on SoC variant. Nothing is going to break down if some are missing. From the controller perspective, the description given here is correct and the inputs are optional. The more generic question is how do we deal with multiple, independent and optional ressources ? Because then, the order in which they appear cannot be predicted. > >> I guess the question is how do you recommend to model that ? >> I can think of 'Anyof' with all the optional clocks repeated 28 times >> but that would be fairly ugly. > > > Best regards, > Krzysztof
On Thu, Aug 10, 2023 at 09:51:05AM +0200, Jerome Brunet wrote: > > On Thu 10 Aug 2023 at 09:46, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > > On 10/08/2023 09:32, Jerome Brunet wrote: > >>>>> Then why do you have this huge, apparently unnecessary, oneOf? If it's > >>>>> the same, then drop the oneOf and make number of clocks fixed. > >>>> > >>>> But as far as I understand the number of clocks is not fixed. As Jerome pointed > >>>> out in the other post, it can have any combination of clocks and range from 1 > >>>> up to 11, where 'pclk' is always 1st clock. > >>>> I currently have no idea how to constraint that, despite limiting the number > >>>> of clock-names. > >>> > >>> The same as in all other clock controllers (was also present on my list > >>> of useful patterns - Variable length arrays (per variant)): > >>> https://elixir.bootlin.com/linux/v5.19-rc6/source/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml#L57 > >> > >> In the example provided, the number and list of clocks required by each > >> controller variant is fixed, if I'm reading it correctly > >> > >> Here the controller (regardless of the variant) accepts a maximum 29 > >> clock inputs. Only pclk is required. It is valid to have any of 28 > >> optional clocks at index 2, 3, etc ... > > > > I actually doubt that it is optional. These are valid clock inputs. I > > could imagine they are optional depending on the use-case, like some > > block being turned off or on... but then still the clock is there, just > > not actively used. > > > > Aren't you now describing existing Linux driver? > > They are valid inputs but not required. It is valid (and expected) to > have a fair share of them not connected. The slave clocks just don't exist > most of the time, and the IP can totally accept unwired master clock > inputs on SoC variant. Nothing is going to break down if some are > missing. > > >From the controller perspective, the description given here is correct > and the inputs are optional. > > The more generic question is how do we deal with multiple, > independent and optional ressources ? Because then, the order in which > they appear cannot be predicted. phandle values of 0 or -1 are treated as "NULL" entries. Rob
diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt deleted file mode 100644 index 3a8948c04bc9..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt +++ /dev/null @@ -1,59 +0,0 @@ -* Amlogic AXG Audio Clock Controllers - -The Amlogic AXG audio clock controller generates and supplies clock to the -other elements of the audio subsystem, such as fifos, i2s, spdif and pdm -devices. - -Required Properties: - -- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, - "amlogic,g12a-audio-clkc" for G12A, - "amlogic,sm1-audio-clkc" for S905X3. -- reg : physical base address of the clock controller and length of - memory mapped region. -- clocks : a list of phandle + clock-specifier pairs for the clocks listed - in clock-names. -- clock-names : must contain the following: - * "pclk" - Main peripheral bus clock - may contain the following: - * "mst_in[0-7]" - 8 input plls to generate clock signals - * "slv_sclk[0-9]" - 10 slave bit clocks provided by external - components. - * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external - components. -- resets : phandle of the internal reset line -- #clock-cells : should be 1. -- #reset-cells : should be 1 on the g12a (and following) soc family - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be -used in device tree sources. - -Example: - -clkc_audio: clock-controller@0 { - compatible = "amlogic,axg-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - resets = <&reset RESET_AUDIO>; -}; diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml new file mode 100644 index 000000000000..629fa3a81cf7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic AXG Audio Clock Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Jerome Brunet <jbrunet@baylibre.com> + - Jian Hu <jian.hu@jian.hu.com> + - Dmitry Rokosov <ddrokosov@sberdevices.ru> + +description: + The Amlogic AXG audio clock controller generates and supplies clock to the + other elements of the audio subsystem, such as fifos, i2s, spdif and pdm + devices. + +properties: + compatible: + enum: + - amlogic,axg-audio-clkc + - amlogic,g12a-audio-clkc + - amlogic,sm1-audio-clkc + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 11 + + clock-names: + oneOf: + - const: pclk + - items: + - const: pclk + - const: mst_in0 + - const: mst_in1 + - const: mst_in2 + - const: mst_in3 + - const: mst_in4 + - const: mst_in5 + - const: mst_in6 + - const: mst_in7 + - items: + - const: pclk + - const: slv_sclk0 + - const: slv_sclk1 + - const: slv_sclk2 + - const: slv_sclk3 + - const: slv_sclk4 + - const: slv_sclk5 + - const: slv_sclk6 + - const: slv_sclk7 + - const: slv_sclk8 + - const: slv_sclk9 + - items: + - const: pclk + - const: slv_lrclk0 + - const: slv_lrclk1 + - const: slv_lrclk2 + - const: slv_lrclk3 + - const: slv_lrclk4 + - const: slv_lrclk5 + - const: slv_lrclk6 + - const: slv_lrclk7 + - const: slv_lrclk8 + - const: slv_lrclk9 + + resets: + description: internal reset line + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + - resets + +allOf: + - if: + properties: + compatible: + contains: + enum: + - amlogic,g12a-audio-clkc + - amlogic,sm1-audio-clkc + then: + required: + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/axg-clkc.h> + #include <dt-bindings/reset/amlogic,meson-axg-reset.h> + apb { + #address-cells = <2>; + #size-cells = <2>; + + clkc_audio: clock-controller@0 { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + resets = <&reset RESET_AUDIO>; + }; + };
Convert Amlogic AXG Audio Clock Controller binding to yaml. Signed-off-by: Alexander Stein <alexander.stein@mailbox.org> --- As it is the same directory I picked the same maintainers as Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml. I'm not 100% sure about the optional clocks constraints. As mentioned in the .txt version only pclk is mandatory, others are optional. .../bindings/clock/amlogic,axg-audio-clkc.txt | 59 -------- .../clock/amlogic,axg-audio-clkc.yaml | 136 ++++++++++++++++++ 2 files changed, 136 insertions(+), 59 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml