| Message ID | 20230803042738.5937-1-parri.andrea@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 4eb2eb1b4c0eb07793c240744843498564a67b83 |
| Headers | show |
| Series | [v2] riscv,mmio: Fix readX()-to-delay() ordering | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 471aba2e4760 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 4 and now 4 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 2662 this patch: 2662 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 14984 this patch: 14984 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 31 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
Hello: This patch was applied to riscv/linux.git (fixes) by Palmer Dabbelt <palmer@rivosinc.com>: On Thu, 3 Aug 2023 06:27:38 +0200 you wrote: > Section 2.1 of the Platform Specification [1] states: > > Unless otherwise specified by a given I/O device, I/O devices are on > ordering channel 0 (i.e., they are point-to-point strongly ordered). > > which is not sufficient to guarantee that a readX() by a hart completes > before a subsequent delay() on the same hart (cf. memory-barriers.txt, > "Kernel I/O barrier effects"). > > [...] Here is the summary with links: - [v2] riscv,mmio: Fix readX()-to-delay() ordering https://git.kernel.org/riscv/c/4eb2eb1b4c0e You are awesome, thank you!
On Thu, 03 Aug 2023 06:27:38 +0200, Andrea Parri wrote: > Section 2.1 of the Platform Specification [1] states: > > Unless otherwise specified by a given I/O device, I/O devices are on > ordering channel 0 (i.e., they are point-to-point strongly ordered). > > which is not sufficient to guarantee that a readX() by a hart completes > before a subsequent delay() on the same hart (cf. memory-barriers.txt, > "Kernel I/O barrier effects"). > > [...] Applied, thanks! [1/1] riscv,mmio: Fix readX()-to-delay() ordering https://git.kernel.org/palmer/c/4eb2eb1b4c0e Best regards,
diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index aff6c33ab0c08..4c58ee7f95ecf 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -101,9 +101,9 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * Relaxed I/O memory access primitives. These follow the Device memory * ordering rules but do not guarantee any ordering relative to Normal memory * accesses. These are defined to order the indicated access (either a read or - * write) with all other I/O memory accesses. Since the platform specification - * defines that all I/O regions are strongly ordered on channel 2, no explicit - * fences are required to enforce this ordering. + * write) with all other I/O memory accesses to the same peripheral. Since the + * platform specification defines that all I/O regions are strongly ordered on + * channel 0, no explicit fences are required to enforce this ordering. */ /* FIXME: These are now the same as asm-generic */ #define __io_rbr() do {} while (0) @@ -125,14 +125,14 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #endif /* - * I/O memory access primitives. Reads are ordered relative to any - * following Normal memory access. Writes are ordered relative to any prior - * Normal memory access. The memory barriers here are necessary as RISC-V + * I/O memory access primitives. Reads are ordered relative to any following + * Normal memory read and delay() loop. Writes are ordered relative to any + * prior Normal memory write. The memory barriers here are necessary as RISC-V * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory") -#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory") +#define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); }) +#define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) #define __io_aw() mmiowb_set_pending() #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
Section 2.1 of the Platform Specification [1] states: Unless otherwise specified by a given I/O device, I/O devices are on ordering channel 0 (i.e., they are point-to-point strongly ordered). which is not sufficient to guarantee that a readX() by a hart completes before a subsequent delay() on the same hart (cf. memory-barriers.txt, "Kernel I/O barrier effects"). Set the I(nput) bit in __io_ar() to restore the ordering, align inline comments. [1] https://github.com/riscv/riscv-platform-specs Signed-off-by: Andrea Parri <parri.andrea@gmail.com> --- Changes since v1: https://lore.kernel.org/lkml/20230711133348.151383-1-parri.andrea@gmail.com/ - surrendered to the intricacies of NOMMU/RV32 builds: dropping #2 (takers are welcome! ;-) ) arch/riscv/include/asm/mmio.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)