| Message ID | 20230728124609.2911830-7-animesh.manna@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Panel replay phase1 implementation | expand |
On Fri, 2023-07-28 at 18:16 +0530, Animesh Manna wrote: > TRANS_DP2_CTL register is programmed to enable panel replay from > source > and sink is enabled through panel replay dpcd configuration address. > > Bspec: 1407940617 > > v1: Initial version. > v2: > - Use pr_* flags instead psr_* flags. [Jouni] > - Remove intel_dp_is_edp check as edp1.5 also has panel replay. > [Jouni] > > v3: cover letter updated and selective fetch condition check is added > before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni] > > Note: Initial plan is to enable panel replay in full-screen live > active > frame update mode. In a incremental approach panel replay will be > enabled > in selctive update mode if there is any gap in curent implementation. > > Cc: Jouni Högander <jouni.hogander@intel.com> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_psr.c | 32 ++++++++++++++++- > -- > 2 files changed, 29 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 1ff7e6c03b44..41fbd49393f3 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1696,6 +1696,7 @@ struct intel_psr { > u16 su_y_granularity; > bool source_panel_replay_support; > bool sink_panel_replay_support; > + bool pr_enabled; > u32 dc3co_exitline; > u32 dc3co_exit_delay; > struct delayed_work dc3co_work; > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index f6b00abe92d4..244fb336f6bc 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -599,8 +599,14 @@ static void intel_psr_enable_sink(struct > intel_dp *intel_dp) > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > u8 dpcd_val = DP_PSR_ENABLE; > > - /* Enable ALPM at sink for psr2 */ > + if (intel_dp->psr.pr_enabled) { > + drm_dp_dpcd_writeb(&intel_dp->aux, > PANEL_REPLAY_CONFIG, > + DP_PANEL_REPLAY_ENABLE); > + return; > + } > + > if (intel_dp->psr.psr2_enabled) { > + /* Enable ALPM at sink for psr2 */ > drm_dp_dpcd_writeb(&intel_dp->aux, > DP_RECEIVER_ALPM_CONFIG, > DP_ALPM_ENABLE | > > DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); > @@ -750,6 +756,18 @@ static int psr2_block_count(struct intel_dp > *intel_dp) > return psr2_block_count_lines(intel_dp) / 4; > } > > +static void dg2_activate_panel_replay(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + > + if (intel_dp->psr.psr2_sel_fetch_enabled) > + intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp- > >psr.transcoder), > + 0, > ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE); This is definitely not right thing to do here. It will be taken care by intel_psr2_program_trans_man_trk_ctl when we enable selective update for panel replay. BR, Jouni Högander > + > + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp- > >psr.transcoder), 0, > + TRANS_DP2_PANEL_REPLAY_ENABLE); > +} > + > static void hsw_activate_psr2(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > @@ -1361,8 +1379,10 @@ static void intel_psr_activate(struct intel_dp > *intel_dp) > > lockdep_assert_held(&intel_dp->psr.lock); > > - /* psr1 and psr2 are mutually exclusive.*/ > - if (intel_dp->psr.psr2_enabled) > + /* psr1, psr2 and panel-replay are mutually exclusive.*/ > + if (intel_dp->psr.pr_enabled) > + dg2_activate_panel_replay(intel_dp); > + else if (intel_dp->psr.psr2_enabled) > hsw_activate_psr2(intel_dp); > else > hsw_activate_psr1(intel_dp); > @@ -1541,6 +1561,7 @@ static void intel_psr_enable_locked(struct > intel_dp *intel_dp, > drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); > > intel_dp->psr.psr2_enabled = crtc_state->has_psr2; > + intel_dp->psr.pr_enabled = crtc_state->has_pr; > intel_dp->psr.busy_frontbuffer_bits = 0; > intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)- > >pipe; > intel_dp->psr.transcoder = crtc_state->cpu_transcoder; > @@ -1586,7 +1607,10 @@ static void intel_psr_exit(struct intel_dp > *intel_dp) > return; > } > > - if (intel_dp->psr.psr2_enabled) { > + if (intel_dp->psr.pr_enabled) { > + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp- > >psr.transcoder), > + TRANS_DP2_PANEL_REPLAY_ENABLE, 0); > + } else if (intel_dp->psr.psr2_enabled) { > tgl_disallow_dc3co_on_psr2_exit(intel_dp); > > val = intel_de_rmw(dev_priv, > EDP_PSR2_CTL(cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1ff7e6c03b44..41fbd49393f3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1696,6 +1696,7 @@ struct intel_psr { u16 su_y_granularity; bool source_panel_replay_support; bool sink_panel_replay_support; + bool pr_enabled; u32 dc3co_exitline; u32 dc3co_exit_delay; struct delayed_work dc3co_work; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f6b00abe92d4..244fb336f6bc 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -599,8 +599,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 dpcd_val = DP_PSR_ENABLE; - /* Enable ALPM at sink for psr2 */ + if (intel_dp->psr.pr_enabled) { + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, + DP_PANEL_REPLAY_ENABLE); + return; + } + if (intel_dp->psr.psr2_enabled) { + /* Enable ALPM at sink for psr2 */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); @@ -750,6 +756,18 @@ static int psr2_block_count(struct intel_dp *intel_dp) return psr2_block_count_lines(intel_dp) / 4; } +static void dg2_activate_panel_replay(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + if (intel_dp->psr.psr2_sel_fetch_enabled) + intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), + 0, ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE); + + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, + TRANS_DP2_PANEL_REPLAY_ENABLE); +} + static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -1361,8 +1379,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp) lockdep_assert_held(&intel_dp->psr.lock); - /* psr1 and psr2 are mutually exclusive.*/ - if (intel_dp->psr.psr2_enabled) + /* psr1, psr2 and panel-replay are mutually exclusive.*/ + if (intel_dp->psr.pr_enabled) + dg2_activate_panel_replay(intel_dp); + else if (intel_dp->psr.psr2_enabled) hsw_activate_psr2(intel_dp); else hsw_activate_psr1(intel_dp); @@ -1541,6 +1561,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); intel_dp->psr.psr2_enabled = crtc_state->has_psr2; + intel_dp->psr.pr_enabled = crtc_state->has_pr; intel_dp->psr.busy_frontbuffer_bits = 0; intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; intel_dp->psr.transcoder = crtc_state->cpu_transcoder; @@ -1586,7 +1607,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp) return; } - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.pr_enabled) { + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), + TRANS_DP2_PANEL_REPLAY_ENABLE, 0); + } else if (intel_dp->psr.psr2_enabled) { tgl_disallow_dc3co_on_psr2_exit(intel_dp); val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
TRANS_DP2_CTL register is programmed to enable panel replay from source and sink is enabled through panel replay dpcd configuration address. Bspec: 1407940617 v1: Initial version. v2: - Use pr_* flags instead psr_* flags. [Jouni] - Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni] v3: cover letter updated and selective fetch condition check is added before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni] Note: Initial plan is to enable panel replay in full-screen live active frame update mode. In a incremental approach panel replay will be enabled in selctive update mode if there is any gap in curent implementation. Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 32 ++++++++++++++++--- 2 files changed, 29 insertions(+), 4 deletions(-)