| Message ID | 20230809115516.214537-11-ajones@ventanamicro.com (mailing list archive) |
|---|---|
| State | Superseded |
| Commit | d45243f8c239e397331a98fd098199e40829cfeb |
| Headers | show |
| Series | RISC-V: Enable cbo.zero in usermode | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 174e8ac0272d |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 4 and now 4 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 230 this patch: 230 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 876 this patch: 876 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 12 this patch: 12 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | CHECK: Prefer using the BIT macro |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Wed, Aug 9, 2023 at 4:55 AM Andrew Jones <ajones@ventanamicro.com> wrote: > > Expose Zicboz through hwprobe and also provide a key to extract its > respective block size. Opportunistically add a macro and apply it to > current extensions in order to avoid duplicating code. > > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Evan Green <evan@rivosinc.com>
On Wed, Aug 09, 2023 at 01:55:20PM +0200, Andrew Jones wrote: > Expose Zicboz through hwprobe and also provide a key to extract its > respective block size. Opportunistically add a macro and apply it to > current extensions in order to avoid duplicating code. > > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> > --- > Documentation/riscv/hwprobe.rst | 6 ++++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > arch/riscv/kernel/sys_riscv.c | 41 ++++++++++++++++++--------- > 4 files changed, 36 insertions(+), 15 deletions(-) > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > index 933c715065d6..6a17c2872660 100644 > --- a/Documentation/riscv/hwprobe.rst > +++ b/Documentation/riscv/hwprobe.rst > @@ -77,6 +77,9 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined > in version 1.0 of the Bit-Manipulation ISA extensions. > > + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as > + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > @@ -97,3 +100,6 @@ The following keys are defined: > > * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are > not supported at all and will generate a misaligned address fault. > + > +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > + represents the size of the Zicboz block in bytes. > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > index 78936f4ff513..39df8604fea1 100644 > --- a/arch/riscv/include/asm/hwprobe.h > +++ b/arch/riscv/include/asm/hwprobe.h > @@ -8,6 +8,6 @@ > > #include <uapi/asm/hwprobe.h> > > -#define RISCV_HWPROBE_MAX_KEY 5 > +#define RISCV_HWPROBE_MAX_KEY 6 > > #endif > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 006bfb48343d..86d08a0e617b 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -29,6 +29,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_EXT_ZBA (1 << 3) > #define RISCV_HWPROBE_EXT_ZBB (1 << 4) > #define RISCV_HWPROBE_EXT_ZBS (1 << 5) > +#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > @@ -36,6 +37,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > +#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > #endif > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > index 26ef5526bfb4..7d970358597b 100644 > --- a/arch/riscv/kernel/sys_riscv.c > +++ b/arch/riscv/kernel/sys_riscv.c > @@ -145,26 +145,33 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > for_each_cpu(cpu, cpus) { > struct riscv_isainfo *isainfo = &hart_isa[cpu]; > > - if (riscv_isa_extension_available(isainfo->isa, ZBA)) > - pair->value |= RISCV_HWPROBE_EXT_ZBA; > - else > - missing |= RISCV_HWPROBE_EXT_ZBA; > - > - if (riscv_isa_extension_available(isainfo->isa, ZBB)) > - pair->value |= RISCV_HWPROBE_EXT_ZBB; > - else > - missing |= RISCV_HWPROBE_EXT_ZBB; > - > - if (riscv_isa_extension_available(isainfo->isa, ZBS)) > - pair->value |= RISCV_HWPROBE_EXT_ZBS; > - else > - missing |= RISCV_HWPROBE_EXT_ZBS; > +#define EXT_KEY(ext) \ > + do { \ > + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_EXT_##ext)) \ > + pair->value |= RISCV_HWPROBE_EXT_##ext; \ > + else \ > + missing |= RISCV_HWPROBE_EXT_##ext; \ > + } while (false) Would you mind adding a comment here that using this macro is only permitted for extensions that can be used by userspace regardless of kernel config options? > + EXT_KEY(ZBA); > + EXT_KEY(ZBB); > + EXT_KEY(ZBS); > + EXT_KEY(ZICBOZ); > +#undef EXT_KEY > } > > /* Now turn off reporting features if any CPU is missing it. */ > pair->value &= ~missing; > }
On Thu, Aug 10, 2023 at 10:49:59AM +0100, Conor Dooley wrote: > On Wed, Aug 09, 2023 at 01:55:20PM +0200, Andrew Jones wrote: > > Expose Zicboz through hwprobe and also provide a key to extract its > > respective block size. Opportunistically add a macro and apply it to > > current extensions in order to avoid duplicating code. > > > > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> > > --- > > Documentation/riscv/hwprobe.rst | 6 ++++ > > arch/riscv/include/asm/hwprobe.h | 2 +- > > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > > arch/riscv/kernel/sys_riscv.c | 41 ++++++++++++++++++--------- > > 4 files changed, 36 insertions(+), 15 deletions(-) > > > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > > index 933c715065d6..6a17c2872660 100644 > > --- a/Documentation/riscv/hwprobe.rst > > +++ b/Documentation/riscv/hwprobe.rst > > @@ -77,6 +77,9 @@ The following keys are defined: > > * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined > > in version 1.0 of the Bit-Manipulation ISA extensions. > > > > + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as > > + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. > > + > > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > > information about the selected set of processors. > > > > @@ -97,3 +100,6 @@ The following keys are defined: > > > > * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are > > not supported at all and will generate a misaligned address fault. > > + > > +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > > + represents the size of the Zicboz block in bytes. > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > > index 78936f4ff513..39df8604fea1 100644 > > --- a/arch/riscv/include/asm/hwprobe.h > > +++ b/arch/riscv/include/asm/hwprobe.h > > @@ -8,6 +8,6 @@ > > > > #include <uapi/asm/hwprobe.h> > > > > -#define RISCV_HWPROBE_MAX_KEY 5 > > +#define RISCV_HWPROBE_MAX_KEY 6 > > > > #endif > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > index 006bfb48343d..86d08a0e617b 100644 > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > @@ -29,6 +29,7 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_EXT_ZBA (1 << 3) > > #define RISCV_HWPROBE_EXT_ZBB (1 << 4) > > #define RISCV_HWPROBE_EXT_ZBS (1 << 5) > > +#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) > > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > > @@ -36,6 +37,7 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) > > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > > +#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > > > #endif > > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > > index 26ef5526bfb4..7d970358597b 100644 > > --- a/arch/riscv/kernel/sys_riscv.c > > +++ b/arch/riscv/kernel/sys_riscv.c > > @@ -145,26 +145,33 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > > for_each_cpu(cpu, cpus) { > > struct riscv_isainfo *isainfo = &hart_isa[cpu]; > > > > - if (riscv_isa_extension_available(isainfo->isa, ZBA)) > > - pair->value |= RISCV_HWPROBE_EXT_ZBA; > > - else > > - missing |= RISCV_HWPROBE_EXT_ZBA; > > - > > - if (riscv_isa_extension_available(isainfo->isa, ZBB)) > > - pair->value |= RISCV_HWPROBE_EXT_ZBB; > > - else > > - missing |= RISCV_HWPROBE_EXT_ZBB; > > - > > - if (riscv_isa_extension_available(isainfo->isa, ZBS)) > > - pair->value |= RISCV_HWPROBE_EXT_ZBS; > > - else > > - missing |= RISCV_HWPROBE_EXT_ZBS; > > +#define EXT_KEY(ext) \ > > + do { \ > > + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_EXT_##ext)) \ > > + pair->value |= RISCV_HWPROBE_EXT_##ext; \ > > + else \ > > + missing |= RISCV_HWPROBE_EXT_##ext; \ > > + } while (false) > > Would you mind adding a comment here that using this macro is only > permitted for extensions that can be used by userspace regardless of kernel > config options? I can do that. Then, as part of the "extension available" API rework, we can maybe drop the comment when we use the new call, which will be documented to say that as well. Thanks, drew > > > + EXT_KEY(ZBA); > > + EXT_KEY(ZBB); > > + EXT_KEY(ZBS); > > + EXT_KEY(ZICBOZ); > > +#undef EXT_KEY > > } > > > > /* Now turn off reporting features if any CPU is missing it. */ > > pair->value &= ~missing; > > }
On Thu, Aug 10, 2023 at 12:57:30PM +0200, Andrew Jones wrote: > On Thu, Aug 10, 2023 at 10:49:59AM +0100, Conor Dooley wrote: > > On Wed, Aug 09, 2023 at 01:55:20PM +0200, Andrew Jones wrote: > > > +#define EXT_KEY(ext) \ > > > + do { \ > > > + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_EXT_##ext)) \ > > > + pair->value |= RISCV_HWPROBE_EXT_##ext; \ > > > + else \ > > > + missing |= RISCV_HWPROBE_EXT_##ext; \ > > > + } while (false) > > > > Would you mind adding a comment here that using this macro is only > > permitted for extensions that can be used by userspace regardless of kernel > > config options? > > I can do that. Then, as part of the "extension available" API rework, we > can maybe drop the comment when we use the new call, which will be > documented to say that as well. Yeah, exactly.
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 933c715065d6..6a17c2872660 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -77,6 +77,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. @@ -97,3 +100,6 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are not supported at all and will generate a misaligned address fault. + +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which + represents the size of the Zicboz block in bytes. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 78936f4ff513..39df8604fea1 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include <uapi/asm/hwprobe.h> -#define RISCV_HWPROBE_MAX_KEY 5 +#define RISCV_HWPROBE_MAX_KEY 6 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 006bfb48343d..86d08a0e617b 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -29,6 +29,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBA (1 << 3) #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) @@ -36,6 +37,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) +#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 26ef5526bfb4..7d970358597b 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -145,26 +145,33 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, for_each_cpu(cpu, cpus) { struct riscv_isainfo *isainfo = &hart_isa[cpu]; - if (riscv_isa_extension_available(isainfo->isa, ZBA)) - pair->value |= RISCV_HWPROBE_EXT_ZBA; - else - missing |= RISCV_HWPROBE_EXT_ZBA; - - if (riscv_isa_extension_available(isainfo->isa, ZBB)) - pair->value |= RISCV_HWPROBE_EXT_ZBB; - else - missing |= RISCV_HWPROBE_EXT_ZBB; - - if (riscv_isa_extension_available(isainfo->isa, ZBS)) - pair->value |= RISCV_HWPROBE_EXT_ZBS; - else - missing |= RISCV_HWPROBE_EXT_ZBS; +#define EXT_KEY(ext) \ + do { \ + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_EXT_##ext)) \ + pair->value |= RISCV_HWPROBE_EXT_##ext; \ + else \ + missing |= RISCV_HWPROBE_EXT_##ext; \ + } while (false) + + EXT_KEY(ZBA); + EXT_KEY(ZBB); + EXT_KEY(ZBS); + EXT_KEY(ZICBOZ); +#undef EXT_KEY } /* Now turn off reporting features if any CPU is missing it. */ pair->value &= ~missing; } +static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext) +{ + struct riscv_hwprobe pair; + + hwprobe_isa_ext0(&pair, cpus); + return (pair.value & ext); +} + static u64 hwprobe_misaligned(const struct cpumask *cpus) { int cpu; @@ -215,6 +222,12 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, pair->value = hwprobe_misaligned(cpus); break; + case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE: + pair->value = 0; + if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ)) + pair->value = riscv_cboz_block_size; + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0
Expose Zicboz through hwprobe and also provide a key to extract its respective block size. Opportunistically add a macro and apply it to current extensions in order to avoid duplicating code. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- Documentation/riscv/hwprobe.rst | 6 ++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 41 ++++++++++++++++++--------- 4 files changed, 36 insertions(+), 15 deletions(-)