diff mbox series

[v3,06/11] KVM: selftests: Test consistency of CPUID with num of fixed counters

Message ID 20230814115108.45741-7-cloudliang@tencent.com (mailing list archive)
State New, archived
Headers show
Series KVM: selftests: Test the consistency of the PMU's CPUID and its features | expand

Commit Message

Jinrong Liang Aug. 14, 2023, 11:51 a.m. UTC 
From: Jinrong Liang <cloudliang@tencent.com>

Add test to check if non-existent counters can be accessed in guest after
determining the number of Intel generic performance counters by CPUID.
Per SDM, fixed-function performance counter 'i' is supported if ECX[i] ||
(EDX[4:0] > i). KVM doesn't emulate more counters than it can support.

Co-developed-by: Like Xu <likexu@tencent.com>
Signed-off-by: Like Xu <likexu@tencent.com>
Signed-off-by: Jinrong Liang <cloudliang@tencent.com>
---
 .../kvm/x86_64/pmu_basic_functionality_test.c | 41 +++++++++++++++++++
 1 file changed, 41 insertions(+)

Comments

Sean Christopherson Aug. 17, 2023, 11:04 p.m. UTC | #1 
On Mon, Aug 14, 2023, Jinrong Liang wrote:
> @@ -239,6 +272,14 @@ static void intel_test_counters_num(void)
>  		if (!perf_caps[i])
>  			test_oob_gp_counter(0, 2, perf_caps[i], 0);
>  	}
> +
> +	for (ecx = 0;
> +	     ecx <= kvm_cpu_property(X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK) + 1;

This is the perfect time to use a local variable:

	for (ecx = 0; ecx <= fixed_counters_bitmask; ecx++)

> +	     ecx++) {
> +		intel_test_oob_fixed_ctr(0, ecx, GP_VECTOR);
> +		intel_test_oob_fixed_ctr(nr_fixed_counters, ecx, GP_VECTOR);
> +		intel_test_oob_fixed_ctr(nr_fixed_counters + 1, ecx, GP_VECTOR);
> +	}
>  }
>  
>  int main(int argc, char *argv[])
> -- 
> 2.39.3
>
diff mbox series

Patch

diff --git a/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c b/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
index b86033e51d5c..db1c1230700a 100644
--- a/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
+++ b/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
@@ -212,10 +212,43 @@  static void test_oob_gp_counter(uint8_t eax_gp_num, uint8_t offset,
 	kvm_vm_free(vm);
 }
 
+static void intel_test_oob_fixed_ctr(uint8_t edx_fixed_num,
+				     uint32_t fixed_bitmask, uint64_t expected)
+{
+	uint8_t idx = edx_fixed_num;
+	struct kvm_vcpu *vcpu;
+	uint64_t msr_val = 0;
+	struct kvm_vm *vm;
+	bool visible;
+
+	vm = pmu_vm_create_with_one_vcpu(&vcpu, guest_wr_and_rd_msrs);
+
+	vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK,
+				fixed_bitmask);
+	vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_FIXED_COUNTERS,
+				edx_fixed_num);
+
+	visible = fixed_counter_is_supported(vcpu, idx);
+
+	/* KVM doesn't emulate more fixed counters than it can support. */
+	if (idx >= kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS))
+		visible = false;
+
+	vcpu_args_set(vcpu, 3, MSR_CORE_PERF_FIXED_CTR0, idx, 1);
+	if (visible) {
+		while (run_vcpu(vcpu, &msr_val) != UCALL_DONE)
+			TEST_ASSERT_EQ(expected, msr_val);
+	}
+
+	kvm_vm_free(vm);
+}
+
 static void intel_test_counters_num(void)
 {
+	uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);
 	uint8_t nr_gp_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);
 	unsigned int i;
+	uint32_t ecx;
 
 	TEST_REQUIRE(nr_gp_counters > 2);
 
@@ -239,6 +272,14 @@  static void intel_test_counters_num(void)
 		if (!perf_caps[i])
 			test_oob_gp_counter(0, 2, perf_caps[i], 0);
 	}
+
+	for (ecx = 0;
+	     ecx <= kvm_cpu_property(X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK) + 1;
+	     ecx++) {
+		intel_test_oob_fixed_ctr(0, ecx, GP_VECTOR);
+		intel_test_oob_fixed_ctr(nr_fixed_counters, ecx, GP_VECTOR);
+		intel_test_oob_fixed_ctr(nr_fixed_counters + 1, ecx, GP_VECTOR);
+	}
 }
 
 int main(int argc, char *argv[])