| Message ID | 20230814133238.741950-2-privatesub2@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for Allwinner PWM on D1/T113s/R329 SoCs | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 174e8ac0272d |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 4 and now 4 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 12 this patch: 12 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Mon, Aug 14, 2023 at 04:32:16PM +0300, Aleksandr Shubin wrote: > Allwinner's D1, T113-S3 and R329 SoCs have a new pwm > controller witch is different from the previous pwm-sun4i. > > The D1 and T113 are identical in terms of peripherals, > they differ only in the architecture of the CPU core, and > even share the majority of their DT. Because of that, > using the same compatible makes sense. > The R329 is a different SoC though, and should have > a different compatible string added, especially as there > is a difference in the number of channels. > > D1 and T113s SoCs have one PWM controller with 8 channels. > R329 SoC has two PWM controllers in both power domains, one of > them has 9 channels (CPUX one) and the other has 6 (CPUS one). > > Add a device tree binding for them. > > Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com> You missed my R-b from the previous version: https://lore.kernel.org/all/20230810-unmasking-sprinkler-d75e728cc0ee@spud/ Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor.
On Mon, 14 Aug 2023 16:32:16 +0300 Aleksandr Shubin <privatesub2@gmail.com> wrote: Hi Aleksandr, > Allwinner's D1, T113-S3 and R329 SoCs have a new pwm > controller witch is different from the previous pwm-sun4i. > > The D1 and T113 are identical in terms of peripherals, > they differ only in the architecture of the CPU core, and > even share the majority of their DT. Because of that, > using the same compatible makes sense. > The R329 is a different SoC though, and should have > a different compatible string added, especially as there > is a difference in the number of channels. > > D1 and T113s SoCs have one PWM controller with 8 channels. > R329 SoC has two PWM controllers in both power domains, one of > them has 9 channels (CPUX one) and the other has 6 (CPUS one). > > Add a device tree binding for them. > > Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com> > --- > .../bindings/pwm/allwinner,sun20i-pwm.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > new file mode 100644 > index 000000000000..9512d4bed322 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner D1, T113-S3 and R329 PWM > + > +maintainers: > + - Aleksandr Shubin <privatesub2@gmail.com> > + > +properties: > + compatible: > + oneOf: > + - const: allwinner,sun20i-d1-pwm > + - items: > + - const: allwinner,sun20i-r329-pwm > + - const: allwinner,sun20i-d1-pwm > + > + reg: > + maxItems: 1 > + > + "#pwm-cells": > + const: 3 > + > + clocks: > + items: > + - description: 24 MHz oscillator > + - description: Bus Clock The manual tells me that the new PWMs can also use APB0 as the input clock, which (finally!) allows PWM frequencies above 24 MHz. So we should have an explicit reference to that clock - even if the bus clock happens to be gated version of APB0. Cheers, Andre > + > + clock-names: > + items: > + - const: hosc > + - const: bus > + > + resets: > + maxItems: 1 > + > + allwinner,pwm-channels: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: The number of PWM channels configured for this instance > + enum: [6, 9] > + > +allOf: > + - $ref: pwm.yaml# > + > + - if: > + properties: > + compatible: > + contains: > + const: allwinner,sun20i-r329-pwm > + > + then: > + required: > + - allwinner,pwm-channels > + > + else: > + properties: > + allwinner,pwm-channels: false > + > +unevaluatedProperties: false > + > +required: > + - compatible > + - reg > + - "#pwm-cells" > + - clocks > + - clock-names > + - resets > + > +examples: > + - | > + #include <dt-bindings/clock/sun20i-d1-ccu.h> > + #include <dt-bindings/reset/sun20i-d1-ccu.h> > + > + pwm: pwm@2000c00 { > + compatible = "allwinner,sun20i-d1-pwm"; > + reg = <0x02000c00 0x400>; > + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>; > + clock-names = "hosc", "bus"; > + resets = <&ccu RST_BUS_PWM>; > + #pwm-cells = <0x3>; > + }; > + > +...
Hi Andre, вт, 22 авг. 2023 г. в 12:49, Andre Przywara <andre.przywara@arm.com>: > > On Mon, 14 Aug 2023 16:32:16 +0300 > Aleksandr Shubin <privatesub2@gmail.com> wrote: > > Hi Aleksandr, > > > Allwinner's D1, T113-S3 and R329 SoCs have a new pwm > > controller witch is different from the previous pwm-sun4i. > > > > The D1 and T113 are identical in terms of peripherals, > > they differ only in the architecture of the CPU core, and > > even share the majority of their DT. Because of that, > > using the same compatible makes sense. > > The R329 is a different SoC though, and should have > > a different compatible string added, especially as there > > is a difference in the number of channels. > > > > D1 and T113s SoCs have one PWM controller with 8 channels. > > R329 SoC has two PWM controllers in both power domains, one of > > them has 9 channels (CPUX one) and the other has 6 (CPUS one). > > > > Add a device tree binding for them. > > > > Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com> > > --- > > .../bindings/pwm/allwinner,sun20i-pwm.yaml | 85 +++++++++++++++++++ > > 1 file changed, 85 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > > > > diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > > new file mode 100644 > > index 000000000000..9512d4bed322 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > > @@ -0,0 +1,85 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Allwinner D1, T113-S3 and R329 PWM > > + > > +maintainers: > > + - Aleksandr Shubin <privatesub2@gmail.com> > > + > > +properties: > > + compatible: > > + oneOf: > > + - const: allwinner,sun20i-d1-pwm > > + - items: > > + - const: allwinner,sun20i-r329-pwm > > + - const: allwinner,sun20i-d1-pwm > > + > > + reg: > > + maxItems: 1 > > + > > + "#pwm-cells": > > + const: 3 > > + > > + clocks: > > + items: > > + - description: 24 MHz oscillator > > + - description: Bus Clock > > The manual tells me that the new PWMs can also use APB0 as the > input clock, which (finally!) allows PWM frequencies above 24 MHz. > So we should have an explicit reference to that clock - even if the bus > clock happens to be gated version of APB0. Should I change it to something like this: pwm: pwm@2000c00 { compatible = "allwinner,sun20i-d1-pwm"; reg = <0x02000c00 0x400>; clocks = <&ccu CLK_BUS_PWM>, <&dcxo>, <&ccu CLK_APB0>; clock-names = "bus", "hosc", "apb0"; resets = <&ccu RST_BUS_PWM>; #pwm-cells = <0x3>; }; > > Cheers, > Andre > > > + > > + clock-names: > > + items: > > + - const: hosc > > + - const: bus > > + > > + resets: > > + maxItems: 1 > > + > > + allwinner,pwm-channels: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: The number of PWM channels configured for this instance > > + enum: [6, 9] > > + > > +allOf: > > + - $ref: pwm.yaml# > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: allwinner,sun20i-r329-pwm > > + > > + then: > > + required: > > + - allwinner,pwm-channels > > + > > + else: > > + properties: > > + allwinner,pwm-channels: false > > + > > +unevaluatedProperties: false > > + > > +required: > > + - compatible > > + - reg > > + - "#pwm-cells" > > + - clocks > > + - clock-names > > + - resets > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/sun20i-d1-ccu.h> > > + #include <dt-bindings/reset/sun20i-d1-ccu.h> > > + > > + pwm: pwm@2000c00 { > > + compatible = "allwinner,sun20i-d1-pwm"; > > + reg = <0x02000c00 0x400>; > > + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>; > > + clock-names = "hosc", "bus"; > > + resets = <&ccu RST_BUS_PWM>; > > + #pwm-cells = <0x3>; > > + }; > > + > > +... > Cheers, Aleksandr
Hi, On 23/08/2023 07:57, Александр Шубин wrote: > Hi Andre, > > вт, 22 авг. 2023 г. в 12:49, Andre Przywara <andre.przywara@arm.com>: >> >> On Mon, 14 Aug 2023 16:32:16 +0300 >> Aleksandr Shubin <privatesub2@gmail.com> wrote: >> >> Hi Aleksandr, >> >>> Allwinner's D1, T113-S3 and R329 SoCs have a new pwm >>> controller witch is different from the previous pwm-sun4i. >>> >>> The D1 and T113 are identical in terms of peripherals, >>> they differ only in the architecture of the CPU core, and >>> even share the majority of their DT. Because of that, >>> using the same compatible makes sense. >>> The R329 is a different SoC though, and should have >>> a different compatible string added, especially as there >>> is a difference in the number of channels. >>> >>> D1 and T113s SoCs have one PWM controller with 8 channels. >>> R329 SoC has two PWM controllers in both power domains, one of >>> them has 9 channels (CPUX one) and the other has 6 (CPUS one). >>> >>> Add a device tree binding for them. >>> >>> Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com> >>> --- >>> .../bindings/pwm/allwinner,sun20i-pwm.yaml | 85 +++++++++++++++++++ >>> 1 file changed, 85 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml >>> new file mode 100644 >>> index 000000000000..9512d4bed322 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml >>> @@ -0,0 +1,85 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Allwinner D1, T113-S3 and R329 PWM >>> + >>> +maintainers: >>> + - Aleksandr Shubin <privatesub2@gmail.com> >>> + >>> +properties: >>> + compatible: >>> + oneOf: >>> + - const: allwinner,sun20i-d1-pwm >>> + - items: >>> + - const: allwinner,sun20i-r329-pwm >>> + - const: allwinner,sun20i-d1-pwm >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + "#pwm-cells": >>> + const: 3 >>> + >>> + clocks: >>> + items: >>> + - description: 24 MHz oscillator >>> + - description: Bus Clock >> >> The manual tells me that the new PWMs can also use APB0 as the >> input clock, which (finally!) allows PWM frequencies above 24 MHz. >> So we should have an explicit reference to that clock - even if the bus >> clock happens to be gated version of APB0. > > Should I change it to something like this: > pwm: pwm@2000c00 { > compatible = "allwinner,sun20i-d1-pwm"; > reg = <0x02000c00 0x400>; > clocks = <&ccu CLK_BUS_PWM>, <&dcxo>, <&ccu CLK_APB0>; > clock-names = "bus", "hosc", "apb0"; > resets = <&ccu RST_BUS_PWM>; > #pwm-cells = <0x3>; > }; Yes, that is what I had in mind! It shouldn't be too hard to add support for this in the driver as well. Thanks! Andre > >> >> Cheers, >> Andre >> >>> + >>> + clock-names: >>> + items: >>> + - const: hosc >>> + - const: bus >>> + >>> + resets: >>> + maxItems: 1 >>> + >>> + allwinner,pwm-channels: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + description: The number of PWM channels configured for this instance >>> + enum: [6, 9] >>> + >>> +allOf: >>> + - $ref: pwm.yaml# >>> + >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + const: allwinner,sun20i-r329-pwm >>> + >>> + then: >>> + required: >>> + - allwinner,pwm-channels >>> + >>> + else: >>> + properties: >>> + allwinner,pwm-channels: false >>> + >>> +unevaluatedProperties: false >>> + >>> +required: >>> + - compatible >>> + - reg >>> + - "#pwm-cells" >>> + - clocks >>> + - clock-names >>> + - resets >>> + >>> +examples: >>> + - | >>> + #include <dt-bindings/clock/sun20i-d1-ccu.h> >>> + #include <dt-bindings/reset/sun20i-d1-ccu.h> >>> + >>> + pwm: pwm@2000c00 { >>> + compatible = "allwinner,sun20i-d1-pwm"; >>> + reg = <0x02000c00 0x400>; >>> + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>; >>> + clock-names = "hosc", "bus"; >>> + resets = <&ccu RST_BUS_PWM>; >>> + #pwm-cells = <0x3>; >>> + }; >>> + >>> +... >> > > Cheers, > Aleksandr >
diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file mode 100644 index 000000000000..9512d4bed322 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Aleksandr Shubin <privatesub2@gmail.com> + +properties: + compatible: + oneOf: + - const: allwinner,sun20i-d1-pwm + - items: + - const: allwinner,sun20i-r329-pwm + - const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: 24 MHz oscillator + - description: Bus Clock + + clock-names: + items: + - const: hosc + - const: bus + + resets: + maxItems: 1 + + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [6, 9] + +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + const: allwinner,sun20i-r329-pwm + + then: + required: + - allwinner,pwm-channels + + else: + properties: + allwinner,pwm-channels: false + +unevaluatedProperties: false + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + - resets + +examples: + - | + #include <dt-bindings/clock/sun20i-d1-ccu.h> + #include <dt-bindings/reset/sun20i-d1-ccu.h> + + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>; + clock-names = "hosc", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <0x3>; + }; + +...
Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i. The D1 and T113 are identical in terms of peripherals, they differ only in the architecture of the CPU core, and even share the majority of their DT. Because of that, using the same compatible makes sense. The R329 is a different SoC though, and should have a different compatible string added, especially as there is a difference in the number of channels. D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one). Add a device tree binding for them. Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com> --- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml